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ds07-13601-5e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16l mb90630a series mb90632a/634a/p634a n description the mb90630a series are 16-bit microcontrollers designed for high speed real-time processing in consumer product applications such as controlling video cameras, vcrs, or copiers. the series uses the f 2 mc*-16l cpu. the chips incorporate an eight channels 10-bit a/d converter, two channels 8-bit d/a converter, uart two channels, two channels serial interface, 8/16-bit up/down counter, 16-bit i/o timer (two channels input capture, four channels output compare, and one channel 16-bit free-run timer). *: f 2 mc stands for fujitsu flexible microcontroller. n features f 2 mc-16l cpu ? minimum execution time: 62.5 ns/4 mhz oscillation (uses pll clock multiplication), maximum multiplier = 4 ? instruction set optimized for controller applications object code compatibility with f 2 mc-16(h) wide range of data types (bit, byte, word, and long word) improved instruction cycles provide increased speed additional addressing modes: 23 modes high code efficiency access mothods (bank access, linear pointer) (continued) n package 100-pin plastic lqfp (fpt-100p-m05) 100-pin plastic qfp (fpt-100p-m06)
2 mb90630a series (continued) high precision operations are enhanced by use of a 32-bit accumulator extended intelligent i/o service (access area extended to 64 kb) maximum memory space: 16 mb ? enhanced high level language (c) and multitasking support insturctions use of a system stack pointer enhanced pointer indirect instructions barrel shift instructions ? improved execution speed: four byte instruction queue ? powerful interrupt function ? automatic data transfer function that does not use insturction (iios) internal peripherals ? rom: 32 kbytes (mb90632a) 64 kbytes (mb90634a) one-time prom: 64 kbytes (mb90p634a) ? ram: 1 kbytes (mb90632a) 2 kbytes (mb90634a) 3 kbytes (mb90p634a) ? general-purpose ports: 82 ports max. ? 10-bit a/d converter (rc successive approximation): eight channels (10-bit resolution, conversion time = 5.2 m s at 4 mhz with a 4 multiplier) ? 8-bit d/a converter two channels (8-bit resolution) ? uart (can also be used as a serial port) two channels ? i/o expansion serial interface two channels ? 8/16-bit ppg (can be set to either 8-bit two channels or 16-bit one channel) one channel ? 16-bit i/o timer one channel (two channels input capture, four channels output compare, and one channel free-run timer) ? clock output generator ? timebase counter/watchdog timer (18-bit) ? low-power consumption modes ? the device types are classified by the initial value of the oscillation stabilization delay time. oscillation stabilization delay time initial value = 2.05 ms: mb90630a series (mb90632a/634a/p634a) ? package: lqfp-100 (qfp-100 planned) ? cmos technology
mb90630a series 3 n product lineup mb90p634a mb90632a mb90634a classification otprom mask rom rom size 64 kbyte 32 kbyte 64 kbyte ram size 3 kbyte 1 kbyte 2 kbyte cpu functions number of instructions : 340 instruction bit length : 8/16 bits instruction length : 1/7 bytes data bit length : 1/4/8/16/32 bits minimum execution time : 62.5 ns/4 mhz (pll multiplier = 4) interrupt processing time : 1000 ns/16 mhz (minimum) ports i/o ports (cmos/ttl) : 82 ports input pull-up resistors available : 24 ports can be set as open-drain outputs : 8 ports package fpt-100p-m05 fpt-100p-m06 a/d converter 10-bit resolution, 5.2 m s conversion time (at 4 mhz with a 4 multiplier) rc successive approximation, 8 channels (multiplexed inputs) d/a converter 8-bit resolution r-2r type, 2 channels (independent) uart full-duplex, double-buffered (8-bit), internal baud rate correction circuit that uses the operating clock nrz-type transfer, supports midi frequencies, 2 channels serial interface 8-bit data register. lsb-first or msb-first operation can be selected. the transfer shift clock can be input externally. the internal shift clock includes a built-in operating clock correction circuit. 1 channel 8/16-bit ppg can operate as two independent channels in 8-bit mode. can also be used as a single-channel 16-bit ppg. 1 channel 8/16-bit up/down counter 6 event inputs. can operate as two independent 8-bit up/down counter channels. can also be used as a single-channel 16-bit counter. includes reload and compare functions. 1 channel 16-bit i/o timer consists of 2 input capture, 4 output compare, and 1 free-run timer. 1 channel timer functions timebase timer/watchdog timer (18-bit) low-power consumption modes includes sleep, stop, and hardware standby functions oscillation stabilization delay time the initial value of the oscillation stabilization delay time is 64 ms. the oscillation stabilization delay time can also be set to 0 ms, 2.05 ms, 8.19 ms, or 64 ms (for an crystal oscillator). the mb90630a series are for far oscillators. external interrupt 8 inputs external interrupt mode (interrupts can be generated from four different types of request signal) pll function selectable multiplier: 1/2/3/4 (set a multiplier that does not exceed the assured operation frequency range.) other v pp is shared with the md2 pin (for eprom programming) parameter part number ()
4 mb90630a series n pin assignment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst pa1/out1 pa0/out0 p97/in1 p96/in0 p95/zin1 p94/bin1 p93/ain1/irq7 p92/zin0 p91/bin0 p90/ain0/irq6 p67/ppg11 p66/ppg10 p65/ckot p64/ppg01 p63/ppg00 p62/sck2 p61/sot2 p60/sin2 p87 p86 p85/irq5 p84/irq4 p83/irq3 p82/irq2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd v ss p32/wrl p33/wrh p34/hrq p35/hak p36/rdy p37/clk p40/sin0 p41/sot0 p42/sck0 p43/sin1 p44/sot1 v cc p45/sck1 p46/adtg p47 p70/sin3 p71/sot3 p72/sck3 dvrh dv ss p73/dao0 p74/dao1 av cc avrh avrl av ss p50/an0 p51/an1 p52/an2 p53/an3 v ss p54/an4 p55/an5 p56/an6 p57/an7 p80/irq0 p81/irq1 md0 md1 md2 hst p21/a17 p20/a16 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss pa4 pa3/out3 pa2/out2 (top view) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 ( fpt-100p-m05 )
mb90630a series 5 1 p20/a16 2 p21/a17 3 p22/a18 4 p23/a19 5 p24/a20 6 p25/a21 7 p26/a22 8 p27/a23 9 p30/ale 10 p31/rd 11 v ss 12 p32/wrl 13 p33/wrh 14 p34/hrq 15 p35/hak 16 p36/rdy 17 p37/clk 18 p40/sin0 19 p41/sot0 20 p42/sck0 21 p43/sin1 22 p44/sot1 23 v cc 24 p45/sck1 25 p46/adtg 26 p47 27 p70/sin3 28 p71/sot3 29 p72/sck3 30 dvrh pa4 pa3/out3 pa2/out2 rst pa1/out1 pa0/out0 p97/in1 p96/in0 p95/zin1 p94/bin1 p93/ain1/irq7 p92/zin0 p91/bin0 p90/ain0/irq6 p67/ppg11 p66/ppg10 p65/ckot p64/ppg01 p63/ppg00 p62/sck2 p61/sot2 p60/sin2 p87 p86 p85/irq5 p84/irq4 p83/irq3 p82/irq2 hst md2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 dv ss 32 p73/da00 33 p74/da01 34 av cc 35 avrh 36 avrl 37 av ss 38 p50/an0 39 p51/an1 40 p52/an2 41 p53/an3 42 v ss 43 p54/an4 44 p55/an5 45 p56/an6 46 p57/an7 47 p80/irq0 48 p81/irq1 49 md0 50 md1 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 (top view) (fpt-100p-m06)
6 mb90630a series n pin description (continued) stbc: incorporates standby control *1: lqfp (fpt-100p-m05) *2: qfp (fpt-100p-m06) pin no. pin name circuit type function lqfp* 1 qfp* 2 80 82 x0 a oscillator pin 81 83 x1 a oscillator pin 50 52 hst c hardware standby input pin 75 77 rst b reset input pin 83 to 90 85 to 92 p00 to p07 d (stbc) general-purpose i/o ports pull-up resistors can be set (rd07 to rd00 = 1) using the pull-up resistor setting register (rdr0). the setting does not apply for ports set as outputs (d07 to d00 = 1: invalid at the output setting). ad00 to ad07 in external bus mode, the pins function as the lower data i/o or lower address outputs (ad00 to ad07). 91 to 98 93 to 100 p10 to p17 d (stbc) general-purpose i/o ports pull-up resistors can be set (rd17 to rd10 = 1) using the pull-up resistor setting register (rdr1). the setting does not apply for ports set as outputs (d17 to d10 = 1: invalid at the output setting). ad08 to ad15 in 16-bit external bus mode, the pins function as the upper data i/o or middle address outputs (ad08 to ad15). 99, 100, 1 to 6 1 to 8 p20 to p27 h (stbc) general-purpose i/o ports in external bus mode, pins for which the corresponding bit in the hacr register is 0 function as the p20 to p27 pins. a16 to a23 in external bus mode, pins for which the corresponding bit in the hacr register is 1 function as the upper address output pins (a16 to a23). 79p30 h (stbc) general-purpose i/o port functions as the ale pin in external bus mode. ale functions as the address latch enable signal. 810p31 h (stbc) general-purpose i/o port functions as the rd pin in external bus mode. rd functions as the read strobe output (rd ). 10 12 p32 h (stbc) general-purpose i/o port functions as the wr pin in external bus mode if the wre bit in the epcr register is 1. wrl functions as the lower data write strobe output (wrl ). 11 13 p33 h (stbc) general-purpose i/o port functions as the wrh pin in 16-bit external bus mode if the wre bit in the epcr register is 1. wrh functions as the upper data write strobe output (wrh ).
mb90630a series 7 (continued) stbc: incorporates standby control *1: lqfp (fpt-100p-m05) *2: qfp (fpt-100p-m06) pin no. pin name circuit type function lqfp* 1 qfp* 2 12 14 p34 h (stbc) general-purpose i/o port functions as the hrq pin in external bus mode if the hde bit in the epcr register is 1. hrq functions as the hold request input pin (hrq). 13 15 p35 h (stbc) general-purpose i/o port functions as the hak pin in external bus mode if the hde bit in the epcr register is 1. hak functions as the hold acknowledge output (hak ) pin. 14 16 p36 h (stbc) general-purpose i/o port functions as the rdy pin in external bus mode if the rye bit in the epcr register is 1. rdy functions as the external ready input (rdy) pin. 15 17 p37 h (stbc) general-purpose i/o port functions as the clk pin in external bus mode if the cke bit in the epcr register is 1. clk functions as the machine cycle clock output (clk) pin. 16 18 p40 g (stbc) general-purpose i/o port when uart0 is operating, the data at the pin is used as the serial input (sin0). can be set as an open-drain output port (od40 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d40 = 0: invalid at the input setting). sin0 functions as the uart0 serial input (sin0). 17 19 p41 f (stbc) general-purpose i/o port functions as the sot0 pin if the soe bit in the umc register is 1. can be set as an open-drain output port (od41 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d41 = 0: invalid at the input setting). sot0 functions as the uart0 serial data output pin (sot0). 18 20 p42 g (stbc) general-purpose i/o port when uart0 is operating in external shift clock mode, the data at the pin is used as the clock input (sck0). also, functions as the sck0 pin if the soe bit in the umc register is 1. can be set as an open-drain output port (od42 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d42 = 0: invalid at the input setting). sck0 functions as the uart0 serial clock i/o pin (sck0).
8 mb90630a series (continued) stbc: incorporates standby control *1: lqfp (fpt-100p-m05) *2: qfp (fpt-100p-m06) pin no. pin name circuit type function lqfp* 1 qfp* 2 19 21 p43 g (stbc) general-purpose i/o port when i/o expansion serial is operating, the data at the pin is used as the serial input (sin1). can be set as an open-drain output port (od43 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d43 = 0: invalid at the input setting). sin1 functions as the serial input for i/o expansion serial data. 20 22 p44 f (stbc) general-purpose i/o port functions as the sot1 pin if the soe bit in the umc register is 1. can be set as an open-drain output port (od44 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d44 = 0: invalid at the input setting). sot1 functions as the output pin (sot1) for i/o expansion serial data. 22 24 p45 g (stbc) general-purpose i/o port when i/o expansion serial is operating in external shift clock mode, the data at the pin is used as the clock input (sck1). also, functions as the sck1 pin if the soe bit in the umc register is 1. can be set as an open-drain output port (od45 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d45 = 0: invalid at the input setting). sck1 functions as the i/o expansion serial clock i/o pin (sck1). 23 25 p46 f (stbc) general-purpose i/o port can be set as an open-drain output port (od46 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d46 = 0: invalid at the input setting). adtg functions as the external trigger input pin for the a/d converter. 24 26 p47 f (stbc) general-purpose i/o port can be set as an open-drain output port (od47 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d47 = 0: invalid at the input setting). 36 to 39, 41 to 44 38 to 41, 43 to 46 p50 to p57 k (stbc) general-purpose i/o ports an0 to an7 the pins are used as analog inputs (an0 to an7) when the a/d converter is operating. 25 27 p70 i (stbc) general-purpose i/o port sin3 functions as the uart1 serial input (sin3). 26 28 p71 h (stbc) general-purpose i/o port sot3 functions as the uart1 serial data output pin (sot3). 27 29 p72 i (stbc) general-purpose i/o port sck3 functions as the uart1 serial clock i/o pin (sck0).
mb90630a series 9 (continued) stbc: incorporates standby control *1: lqfp (fpt-100p-m05) *2: qfp (fpt-100p-m06) pin no. pin name circuit type function lqfp* 1 qfp* 2 30 32 p73 l (stbc) general-purpose i/o port functions as a d/a output pin when dae0 = 1 in the d/a control register (dacr). dao0 functions as d/a output 0 when the d/a converter is operating. 31 33 p74 l (stbc) general-purpose i/o port functions as a d/a output pin when dae1 = 1 in the d/a control register (dacr). dao1 functions as d/a output 1 when the d/a converter is operating. 45 47 p80 i general-purpose i/o port irq0 functions as external interrupt request i/o 0. 46 48 p81 i general-purpose i/o port irq1 functions as external interrupt request i/o 1. 51 53 p82 i general-purpose i/o port irq2 functions as external interrupt request i/o 2. 52 54 p83 i general-purpose i/o port irq3 functions as external interrupt request i/o 3. 53 55 p84 i general-purpose i/o port irq4 functions as external interrupt request i/o 4. 54 56 p85 i general-purpose i/o port irq5 functions as external interrupt request i/o 5. 55 57 p86 h (stbc) general-purpose i/o port this applies in all cases. 56 58 p87 h (stbc) general-purpose i/o port this applies in all cases. 57 59 p60 e (stbc) general-purpose i/o port a pull-up resistor can be set (rd60 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d60 = 1: invalid at the output setting). sin2 functions as a data input pin (sin2) for i/o expansion serial. 58 60 p61 d (stbc) general-purpose i/o port functions as the sot2 pin if the soe bit in the umc register is 1. a pull-up resistor can be set (rd61 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d61 = 1: invalid at the output setting). sot2 functions as an output pin (sot2) for i/o expansion serial data.
10 mb90630a series (continued) stbc: incorporates standby control *1: lqfp (fpt-100p-m05) *2: qfp (fpt-100p-m06) pin no. pin name circuit type function lqfp* 1 qfp* 2 59 61 p62 e (stbc) general-purpose i/o port when i/o expansion serial is operating in external shift clock mode, the data at the pin is used as the clock input (sck2). also, functions as the sck2 pin if the soe bit in the umc register is 1. a pull-up resistor can be set (rd62 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d62 = 1: invalid at the output setting). sck2 functions as the i/o expansion serial clock i/o pin (sck2). 60 62 p63 d (stbc) general-purpose i/o port a pull-up resistor can be set (rd63 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d63 = 1: invalid at the output setting). ppg00 functions as the ppg00 output when ppg output is enabled. 61 63 p64 d (stbc) general-purpose i/o port a pull-up resistor can be set (rd64 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d64 = 1: invalid at the output setting). ppg01 functions as the ppg01 output when ppg output is enabled. 62 64 p65 d (stbc) general-purpose i/o port a pull-up resistor can be set (rd65 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d65 = 1: invalid at the output setting). ckot functions as the ckot output when ckot is operating. 63 65 p66 d (stbc) general-purpose i/o port a pull-up resistor can be set (rd66 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d66 = 1: invalid at the output setting). ppg10 functions as the ppg10 output when ppg output is enabled. 64 66 p67 d (stbc) general-purpose i/o port a pull-up resistor can be set (rd67 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d67 = 1: invalid at the output setting). ppg11 functions as the ppg11 output when ppg output is enabled. 65 67 p90 i general-purpose i/o port ain0 input to channel 0 of the 8/16-bit up/down timer. irq6 functions as an interrupt request input. 66 68 p91 i (stbc) general-purpose i/o port bin0 input to channel 0 of the 8/16-bit up/down timer.
mb90630a series 11 (continued) stbc: incorporates standby control *1: lqfp (fpt-100p-m05) *2: qfp (fpt-100p-m06) pin no. pin name circuit type function lqfp* 1 qfp* 2 67 69 p92 i (stbc) general-purpose i/o port zin0 input to channel 0 of the 8/16-bit up/down timer. 68 70 p93 i general-purpose i/o port ain1 input to channel 1 of the 8/16-bit up/down timer. irq7 functions as an interrupt request input. 69 71 p94 i (stbc) general-purpose i/o port bin1 input to channel 1 of the 8/16-bit up/down timer. 70 72 p95 i (stbc) general-purpose i/o port zin1 input to channel 1 of the 8/16-bit up/down timer. 71 73 p96 i (stbc) general-purpose i/o port in0 trigger input for channel 0 of the input capture. 72 74 p97 i (stbc) general-purpose i/o port in1 trigger input for channel 1 of the input capture. 73 75 pa0 h (stbc) general-purpose i/o port out0 event output for channel 0 of the output compare. 74 76 pa1 h (stbc) general-purpose i/o port out1 event output for channel 1 of the output compare. 76 78 pa2 h (stbc) general-purpose i/o port out2 event output for channel 2 of the output compare. 77 79 pa3 h (stbc) general-purpose i/o port out3 event output for channel 3 of the output compare. 78 80 pa4 h (stbc) general-purpose i/o port 32 34 av cc a/d converter power supply pin 35 37 av ss a/d converter power supply pin 33 35 avrh a/d converter external reference power supply pin 34 36 avrl a/d converter external reference power supply pin 28 30 dvrh d/a converter external reference power supply pin 29 31 dv ss d/a converter power supply pin 47 to 49 49 to 51 md0 to md2 c operating mode selection pins. connect directly to v cc or v ss . 21, 82 23, 84 v cc power supply (5.0 v) input pin 9, 40, 79 11, 42, 81 v ss power supply (0.0 v) input pin
12 mb90630a series n i/o circuit type (continued) type circuit remarks a ? oscillator feedback registance 1 m w (approx.) b ? hysteresis input with pull-up registance 50 k w (approx.) c ? hysteresis input port d ? incorporates pull-up resistor control (for input) registance 50 k w (approx.) ? cmos level i/o e ? incorporates pull-up resistor control (for input) registance 50 k w (approx.) ? cmos level output ? hysteresis input f ? cmos level i/o ? open-drain control signal x1 x0 standby control signal hys hys ctl cmos ctl hys open-drain control signal cmos
mb90630a series 13 (continued) type circuit remarks g ? cmos level output ? hysteresis input ? incorporates open-drain control h ? cmos level i/o i ? cmos level output ? hysteresis input k ? cmos level i/o ? analog input l ? cmos level i/o ? analog output ? shared with d/a outputs m ? incorporates pull-up resistor control (for input) registance 50 k w (approx.) ? cmos level output ? hysteresis input hys open-drain control signal cmos hys cmos analog input cmos d/a output ctl hys
14 mb90630a series n handling devices 1. preventing latch-up latch-up occurs in a cmos ic if a voltage greater than v cc or less than v ss is applied to an input or output pin or if the voltage applied between v cc and v ss exceeds the rating. if latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. therefore, ensure that maximum ratings are not exceeded in circuit operation. for the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage. 2. treatment of unused pins leaving unused input pins unconnected can cause misoperation. always pull-up or pull-down unused pins. 3. external reset input to reliably reset the controller by inputting an l level to the rst pin, ensure that the l level is applied for at least five machine cycles. take particular note when using an external clock input. 4. v cc and v ss pins ensure that all v cc pins are at the same voltage. the same applies for the v ss pins. 5. precautions when using an external clock drive the x0 pin only when using an external clock. 6. a/d converter power supply and the turn-on sequence for analog inputs always turn off the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an7) before turning off the digital power supply (v cc ). when turning the power on or off, ensure that avrh does not exceed av cc . also, when using the analog input pins as input ports, ensure that the input voltage does not exceed av cc . 7. program mode all bits (64 k 16 bits) in the mb90p634a are 1 on delivery from fujitsu or after erasing. to write data, selectively program the desired bits to 0. the value 1 cannot be written electrically. x0 x1 mb90630a ? using an external clock
mb90630a series 15 8. recommended screening conditions high temperature aging is recommended as the pre-assembly screening procedure. 9. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 10. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of 2 momentary fluctuation such as when power is switched. assembly program, verify aging +150 c, 48 hrs. data verification
16 mb90630a series n programming the eprom in the mb90p634a in eprom mode, the mb90p634a function as mbm27c1000 equivalents. by using a dedicated adapter socket, the devices can be programmed using a standard eprom programmer. 1. pin assignment in eprom mode ? pins compatible with the mbm27c1000 (continued) mbm27c1000 mb90p634a pin number pin name pin number pin name 1v pp 49 md2 (v pp ) 2oe10p32 3a1598p17 4a1295p14 5a076p27 6a065p26 7a054p25 8a043p24 9a032p23 10 a02 1 p22 11 a01 100 p21 12a0099p20 13 d00 83 p00 14 d01 84 p01 15 d02 85 p02 16 gnd 32 v cc 31 pgm 11 p33 30 nc 29a1497p16 28a1396p15 27a0891p10 26a0992p11 25a1194p13 24 a16 7 p30 23a1093p12 22 ce 8 p31 21 d07 90 p07
mb90630a series 17 (continued) ? power supply and gnd connection pins mbm27c1000 mb90p634a pin number pin name pin number pin name 20 d06 89 p06 19 d05 88 p05 18 d04 87 p04 17 d03 86 p03 type pin number pin name power supply (v cc )28 50 21, 82 dvrh hst v cc gnd 9 34 35 40 29 75 79 12 13 14 v ss avrl av ss v ss dv ss rst v ss p34 p35 p36
18 mb90630a series ? pins other than mbm27c1000-compatible pins 2. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 pin number pin name treatment 47 48 80 md0 md1 x0 pull-up (4.7 k w ) 81 x1 open 15 16 to 20 22 to 24 25 to 27 30 31 36 to 39 41 to 44 45 46 51 to 56 57 to 64 65 to 72 73 74 76 77 78 p37 p40 to p44 p45 to p47 p70 to p72 p73 p74 p50 to p53 p54 to p57 p80 p81 p82 to p87 p60 to p67 p90 to p97 pa0 pa1 pa2 pa3 pa4 part no. package compatible socket adapter sun hayato co., ltd. mb90p634apfv sqfp-100 rom-100sqf-32dp-16l connect pull-up resistors of approximately 1 m w to each pin
mb90630a series 19 3. programming procedure (1) set the eprom programmer for a mbm27c1000. (2) load the program data between 10000 h and 1ffff h in the eprom programmer. in the mb90p634a, rom addresses ffffff h to ff0000 h in operating mode correspond to addresses 1ffff h to 10000 h in eprom mode. (3) set the mb90p634a, in the adapter socket and connect the adapter socket to the eprom programmer. take care to correctly align the device with the adapter. (4) perform programming. (5) if programming cannot be performed successfully, connect a 0.1 m f or similar capacitor between v cc and gnd and between v pp and gnd. note: as mask rom products (mb90632a, 634a) do not support eprom mode, data cannot be read using an eprom programmer. performing a blank check for other than the above addresses results in either non- eprom addresses being read or the blank check being unable to be performed. ffffff h operating mode eprom mode ff0000 h 1ffff h 10000 h
20 mb90630a series n block diagram clock control circuit ram interrupt controller u/d counter 8 bits 2 (16 bits 1) 8 8 8 8 8 8 8 58 p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p74 p80 to p87 i/o ports cpu f 2 mc-16l series core rom prescaler i/o timers in0, 1 out1 to out3 external interrupts 8 p90 to p97 8 irq0 to irq7 5 pa0 to pa4 4 x0, 1 rst hst ckot (output switching) 1 channel uart 2 channels sin0, 3 sot0, 3 sck0, 3 sin1, 2 sot1, 2 sck1, 2 a/d converter (10 bits) av cc avrh, avrl av ss adtg an0 to an7 communications prescaler d/a converter (8 bits) 2 channels 16-bit input capture 2 channels 16-bit output capture 4 channels 16-bit free-run timer ain0, 1 bin0, 1 zin0, 1 2 2 2 2 2 2 2 2 2 8 dao0, 1 dvrh dv ss p00 to p07 (8 pins) : incorporates a pull-up resistor setting register (for input) p10 to p17 (8 pins) : incorporates a pull-up resistor setting register (for input) p60 to p67 (8 pins) : incorporates a pull-up resistor setting register (for input) p40 to p47 (8 pins) : incorporates an open-drain setting register ppg00, 01 ppg10, 11 8 + 8ppg f 2 mc-16 bus 3 2 2 2 i/o expansion serial interface 2 channels
mb90630a series 21 n f 2 mc-16l cpu programming model ah al dpr pcb dtb usb ssb adb 8 bits 16 bits 32 bits accumulator usp ssp ps pc user stack pointer system stack pointer processor status program counter user stack upper register system stack upper register user stack lower register system stack lower register direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register maximum 32 banks r7 r6 r5 r4 r3 r2 r1 r0 rw3 rw2 rw1 rw0 16 bit 000180 h + rp 10 h ? rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 ilm rp - istnzvc ccr uspcu sspcu uspcl sspcl ? dedicated registers ? general-purpose registers ? processor status (ps)
22 mb90630a series n memory map rom area ffffff h address 1# ff0000 h 010000 h address 2# 000380 h 004000 h 002000 h address 3# 000180 h 000100 h 0000c0 h 000000 h single chip internal rom/external bus external rom/external bus rom area rom area (ff bank image) rom area (ff bank image) ram registers ram registers ram registers peripherals peripherals peripherals : internal : external : no access type address #1 address #2 address #3 mb90632a mb90634a mb90p634a ff8000 h ff0000 h ff0000 h 008000 h 004000 h 004000 h 000500 h 000900 h 000d00 h
mb90630a series 23 n i/o map (continued) address register register name access resource initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx 07 h port 7 data register pdr7 r/w port 7 CCCxxxxx 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx 0a h port a data register pdra r/w port a CCCxxxxx 0b to 0f h reserved area 10 h port 0 direction register ddr0 r/w port 0 0 00 00 00 0 11 h port 1 direction register ddr1 r/w port 1 0 00 00 00 0 12 h port 2 direction register ddr2 r/w port 2 0 00 00 00 0 13 h port 3 direction register ddr3 r/w port 3 0 00 00 00 0 14 h port 4 direction register ddr4 r/w port 4 0 00 00 00 0 15 h port 5 direction register ddr5 r/w port 5 0 00 00 00 0 16 h port 6 direction register ddr6 r/w port 6 0 00 00 00 0 17 h port 7 direction register ddr7 r/w port 7 C CC 00 00 0 18 h port 8 direction register ddr8 r/w port 8 0 00 00 00 0 19 h port 9 direction register ddr9 r/w port 9 0 00 00 00 0 1a h port a direction register ddra r/w port a C CC 00 00 0 1b h port 4 pin register odr4 r/w port 4 0 00 00 00 0 1c h port 0 resistance register rdr0 r/w port 0 0 00 00 00 0 1d h port 1 resistance register rdr1 r/w port 1 0 00 00 00 0 1e h port 6 resistance register rdr6 r/w port 6 0 00 00 00 0 1f h analog input enable register ader r/w port 5, a/d 1 11 11 11 1 20 h serial mode register 0 smr0 r/w uart0 00000000 21 h serial control register 0 scr0 r/w 00000100 22 h serial input register/ serial output register 0 sidr/ sodr0 r/w xxxxxxxx
24 mb90630a series (continued) address register register name access resource initial value 23 h serial status register 0 ssr0 r/w uart0 0 00 01 C0 0 24 h serial mode control status register 0 smcs0 r/w i/o expansion serial interface 0 CCCC0000 25 h serial mode control status register 0 smcs0 r/w 00000010 26 h serial data register 0 sdr0 r/w xxxxxxxx 27 h clock division control register cdcr r/w communications prescaler 0CCC1111 28 h serial mode control status register 1 smcs1 r/w i/o expansion serial interface 1 CCCC0000 29 h serial mode control status register 1 smcs1 r/w 00000010 2a h serial data register 1 sdr1 r/w xxxxxxxx 2b to 2f h reserved area 30 h interrupt/dtp enable register enir r/w dtp/external interrupts 00000000 31 h interrupt/dtp source register eirr r/w xxxxxxxx 32 h request level setting register elvr r/w 00000000 33 h 00000000 34 to 35 h reserved area 36 h control status register adcs1 r/w a/d converter 00000000 37 h adcs2 00000000 38 h data register adcr1 r xxxxxxxx 39 h adcr2 xxxxxxxx 3a h d/a converter data register 0 dat0 r/w d/a converter xxxxxxxx 3b h d/a converter data register 1 dat1 r/w xxxxxxxx 3c h d/a control register 0 dacr0 r/w CCCCCCC0 3d h d/a control register 1 dacr1 r/w CCCCCCC0 3e h clock control register clkr r/w ckot output CCCCC000 3f h reserved area 40 h reload register l (channel 0) prll0 r/w 8/16 bit ppg xxxxxxxx 41 h reload register h (channel 0) prlh0 r/w xxxxxxxx 42 h reload register l (channel 1) prll1 r/w xxxxxxxx 43 h reload register h (channel 1) prlh1 r/w xxxxxxxx 44 h ppg0 operation mode control register ppgc0 r/w 0x000xx1 45 h ppg1 operation mode control register ppgc1 r/w 0x000001 46 h ppg0, 1 output control register ppgoe r/w 0 00 00 00 0 47 to 4f h reserved area 50 h lower compare register channel 0 occp0 r/w 16-bit i/o timer output compare (channel 0 to 3) xxxxxxxx
mb90630a series 25 (continued) address register register name access resource initial value 51 h upper compare register channel 0 occp0 r/w 16-bit i/o timer output compare (channel 0 to 3) xxxxxxxx 52 h lower compare register channel 1 occp1 r/w xxxxxxxx 53 h upper compare register channel 1 xxxxxxxx 54 h lower compare register channel 2 occp2 r/w xxxxxxxx 55 h upper compare register channel 2 xxxxxxxx 56 h lower compare register channel 3 occp3 r/w xxxxxxxx 57 h upper compare register channel 3 xxxxxxxx 58 h compare control status register channel 0 ocs0 r/w CCC00000 59 h compare control status register channel 1 ocs1 r/w 0000CC00 5a h compare control status register channel 2 ocs2 r/w CCC00000 5b h compare control status register channel 3 ocs3 r/w 0000CC00 5c to 5f h reserved area 60 h lower input capture register channel 0 ipcp0 r 16-bit i/o timer input capture (channel 0, 1) xxxxxxxx 61 h upper input capture register channel 0 r xxxxxxxx 62 h lower input capture register channel 1 ipcp1 r xxxxxxxx 63 h upper input capture register channel 1 r xxxxxxxx 64 h input capture control status register ics r/w 0 00 00 00 0 65 h reserved area CCCCCCCC 66 h lower timer data register tcdtl r/w 16-bit i/o timer free-run timer (channel 0, 1) 00000000 67 h upper timer data register tcdth r/w 00000000 68 h timer control status register tccs r/w 0 00 00 00 0 69 to 6f h reserved area 70 h up/down count register channel 0 udcr0 r 8/16-bit up/down timer/counter 00000000 71 h up/down count register channel 1 udcr1 0 00 00 00 0 72 h reload compare register channel 0 rcr0 w 00000000 73 h reload compare register channel 1 rcr1 0 00 00 00 0 74 h counter status register channel 0 csr0 r/w 0 00 00 00 0 75 h reserved area CCCCCCCC 76 h counter control register channel 0 ccrl0 r/w C0000000 77 h ccrh0 00000000 78 h counter status register channel 1 csr1 r/w 0 00 00 00 0 79 h reserved area CCCCCCCC 7a h counter control register channel 1 ccrl1 r/w C 00 00 00 0
26 mb90630a series (continued) address register register name access resource initial value 7b h counter control register channel 1 ccrh1 r/w 8/16-bit up/down timer/counter C0000000 7c to 87 h reserved area 88 h serial mode register 1 smr1 r/w uart1 00000000 89 h serial control register 1 scr1 r/w 00000100 8a h serial input register 1/serial output register 1 sidr1/ sodr1 r/w xxxxxxxx 8b h serial status register 1 ssr1 r/w 0 00 01 C0 0 8c to 9e h reserved area (accessing 90 h to 9e h is prohibited.) 9f h delayed interrupt generation/ clear register dirr r/w delayed interrupt generation module CCCCCCC0 a0 h low-power consumption mode register lpmcr r/w low-power consumption 0 00 11 00 0 a1 h clock selection register ckscr r/w low-power consumption 1 10 01 10 0 a2 to a4 h reserved area a5 h auto-ready function selection register arsr w external pins 0011CC00 a6 h external address output control register hacr w external pins CCCC0000 a7 h bus control signal selection register ecsr w external pins 00 0 0* 0 0C a8 h watchdog timer control register wdtc r/w watchdog timer xxxxx111 a9 h timebase timer control register tbtc r/w timebase timer 1 CC 00 10 0 aa to af h reserved area b0 h interrupt control register 00 icr00 r/w interrupt controller 00000111 b1 h interrupt control register 01 icr01 r/w 0 00 00 11 1 b2 h interrupt control register 02 icr02 r/w 0 00 00 11 1 b3 h interrupt control register 03 icr03 r/w 0 00 00 11 1 b4 h interrupt control register 04 icr04 r/w 0 00 00 11 1 b5 h interrupt control register 05 icr05 r/w 0 00 00 11 1 b6 h interrupt control register 06 icr06 r/w 0 00 00 11 1 b7 h interrupt control register 07 icr07 r/w 0 00 00 11 1 b8 h interrupt control register 08 icr08 r/w 0 00 00 11 1 b9 h interrupt control register 09 icr09 r/w 0 00 00 11 1 ba h interrupt control register 10 icr10 r/w 0 00 00 11 1 bb h interrupt control register 11 icr11 r/w 0 00 00 11 1 bc h interrupt control register 12 icr12 r/w 0 00 00 11 1 bd h interrupt control register 13 icr13 r/w 0 00 00 11 1
mb90630a series 27 (continued) initial values 0: the initial value of this bit is 0. 1: the initial value of this bit is 1. * : the initial value of this bit is 0 or 1. x: the initial value of this bit is undefined. C: this bit is not used. the initial value is undefined. note: areas below address 0000ff h not listed in the table are reserved areas. these addresses are accessed by internal access. no access signals are output on the external bus. address register register name access resource initial value be h interrupt control register 14 icr14 r/w interrupt controller 00000111 bf h interrupt control register 15 icr15 r/w 00000111 c0 to ff h reserved area
28 mb90630a series n interrupt vector and interrupt control register assignments to interrupt sources : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal (no stop request). : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal (stop request present). : indicates that the interrupt request flag is not cleared by the i 2 os interrupt clear signal. note: for resources in which two interrupt sources share the same interrupt number, the i 2 os interrupt clear signal clears both interrupt request flags. interrupt source i 2 os support interrupt vector interrupt control register number address icr address reset #08 ffffdc h int 9 instruction #09 ffffd8 h exception #10 ffffd4 h a/d converter #11 ffffd0 h icr00 0000b0 h dtp 0 (external interrupt 0) #13 ffffc8 h icr01 0000b1 h 16-bit free-run timer (i/o timer) overflow #14 ffffc4 h i/o expansion serial 1 #15 ffffc0 h icr02 0000b2 h dtp 1 (external interrupt 1) #16 ffffbc h i/o expansion serial 2 #17 ffffb8 h icr03 0000b3 h dtp 2 (external interrupt 2) #18 ffffb4 h dtp 3 (external interrupt 3) #19 ffffb0 h icr04 0000b4 h 8/16-bit ppg 0 counter borrow #20 ffffac h 8/16-bit u/d counter 0 compare #21 ffffa8 h icr05 0000b5 h 8/16-bit u/d counter 0 underflow/ overflow, up/down invert #22 ffffa4 h 8/16-bit ppg 1 counter borrow #23 ffffa0 h icr06 0000b6 h dtp 4/5 (external interrupt 4/5) #24 ffff9c h output compare (channel 2) match (i/o timer) #25 ffff98 h icr07 0000b7 h output compare (channel 3) match (i/o timer) #26 ffff94 h dtp 6 (external interrupt 6) #28 ffff8c h icr08 0000b8 h 8/16-bit u/d counter 1 compare #29 ffff88 h icr09 0000b9 h 8/16-bit u/d counter 1 underflow/ overflow, up/down invert #30 ffff84 h input capture (channel 0) read (i/o timer) #31 ffff80 h icr10 0000ba h input capture (channel 1) read (i/o timer) #32 ffff7c h output compare (channel 0) match (i/o timer) #33 ffff78 h icr11 0000bb h output compare (channel 1) match (i/o timer) #34 ffff74 h dtp 7 (external interrupt 7) #36 ffff6c h icr12 0000bc h uart0 receive complete #37 ffff68 h icr13 0000bd h uart1 receive complete #38 ffff64 h uart0 transmit complete #39 ffff60 h icr14 0000be h uart1 transmit complete #40 ffff5c h reserved #41 ffff58 h icr15 0000bf h delayed interrupt #42 ffff54 h
mb90630a series 29 n peripheral resources 1. parallel ports (1) i/o ports each port pin can be specified as either an input or output by its corresponding direction register when the pin is not set for use by a peripheral. when a port is set as an input, reading the data register always reads the value corresponding to the pin level. when a port is set as an output, reading the data register reads the data register latch value. the same applies when reading using a read-modify-write instruction. when used as control outputs, reading the data register reads the control output value, irrespective of the direction register value. note that if a read-modify-write instruction (set bit or similar instruction) is used to set output data in the data register before switching a pin from input to output, the instruction reads the input level at the pin and not the data register latch value. data register direction register data register read data register write direction register write direction register read pin - - - - internal data bus ? block diagram
30 mb90630a series (2) register configuration 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 address: 000000 h address: 000001 h address: 000002 h address: 000003 h address: 000004 h address: 000005 h address: 000006 h address: 000007 h address: 000008 h address: 000009 h address: 00000a h bit p06 p05 p04 p03 p02 p01 p00 p07 p16 p15 p14 p13 p12 p11 p10 p17 p26 p25 p24 p23 p22 p21 p20 p27 p36 p35 p34 p33 p32 p31 p30 p37 p46 p45 p44 p43 p42 p41 p40 p47 p56 p55 p54 p53 p52 p51 p50 p57 p66 p65 p64 p63 p62 p61 p60 p67 p74 p73 p72 p71 p70 p86 p85 p84 p83 p82 p81 p80 p87 p96 p95 p94 p93 p92 p91 p90 p97 pa4 pa3 pa2 pa1 pa0 port 0 data register (pdr0) port 1 data register (pdr1) port 2 data register (pdr2) port 3 data register (pdr3) port 4 data register (pdr4) port 5 data register (pdr5) port 6 data register (pdr6) port 7 data register (pdr7) port 8 data register (pdr8) port 9 data register (pdr9) port a data register (pdra) 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 address: 000010 h address: 000011 h address: 000012 h address: 000013 h address: 000014 h address: 000015 h address: 000016 h address: 000017 h address: 000018 h address: 000019 h address: 00001a h bit d06 d05 d04 d03 d02 d01 d00 d07 d16 d15 d14 d13 d12 d11 d10 d17 d26 d25 d24 d23 d22 d21 d20 d27 d36 d35 d34 d33 d32 d31 d30 d37 d46 d45 d44 d43 d42 d41 d40 d47 d56 d55 d54 d53 d52 d51 d50 d57 d66 d65 d64 d63 d62 d61 d60 d67 d74 d73 d72 d71 d70 d86 d85 d84 d83 d82 d81 d80 d87 d96 d95 d94 d93 d92 d91 d90 d97 da4 da3 da2 da1 da0 port 0 direction register (ddr0) port 1 direction register (ddr1) port 2 direction register (ddr2) port 3 direction register (ddr3) port 4 direction register (ddr4) port 5 direction register (ddr5) port 6 direction register (ddr6) port 7 direction register (ddr7) port 8 direction register (ddr8) port 9 direction register (ddr9) port a direction register (ddra) 15 14 13 12 11 10 9 8 address: 00001b h bit od46 od45 od44 od43 od42 od41 od40 od47 port 4 pin register (odr4) 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 address: 00001c h address: 00001d h address: 00001e h bit rd06 rd05 rd04 rd03 rd02 rd01 rd00 rd07 rd16 rd15 rd14 rd13 rd12 rd11 rd10 rd17 rd66 rd65 rd64 rd63 rd62 rd61 rd60 rd67 port 0 resistor register (rdr0) port 1 resistor register (rdr1) port 6 resistor register (rdr6) 15 14 13 12 11 10 9 8 address: 00001f h bit ade6 ade5 ade4 ade3 ade2 ade1 ade0 ade7 port 5 analog input enable register (ader)
mb90630a series 31 (3) register details ? port data registers * : the operation of reading or writing to i/o ports is slightly different from reading or writing to memory, as follows. ? input mode read: reads the corresponding pin level. write: writes to the output latch. ? output mode read: reads the value of the data register latch. write: the value is output from the corresponding pin. p07 p06 p05 p04 p03 p02 p01 p00 76 54 3210 p17 p16 p15 p14 p13 p12 p11 p10 15 14 13 12 11 10 9 8 p27 p26 p25 p24 p23 p22 p21 p20 76 54 3210 pdr0 address: 000000 h pdr1 address: 000001 h pdr2 address: 000002 h bit bit bit initial value undefined undefined undefined access r/w* r/w* r/w* p37 p36 p35 p34 p33 p32 p31 p30 15 14 13 12 11 10 9 8 p47 p46 p45 p44 p43 p42 p41 p40 76 54 3210 pdr3 address: 000003 h pdr4 address: 000004 h bit bit undefined undefined r/w* r/w* p57 p56 p55 p54 p53 p52 p51 p50 15 14 13 12 11 10 9 8 pdr5 address: 000005 h bit undefined r/w* p67 p66 p65 p64 p63 p62 p61 p60 76 54 3210 p74 p73 p72 p71 p70 15 14 13 12 11 10 9 8 pdr6 address: 000006 h pdr7 address: 000007 h bit bit undefined undefined r/w* r/w* p87 p86 p85 p84 p83 p82 p81 p80 76 54 3210 p97 p96 p95 p94 p93 p92 p91 p90 15 14 13 12 11 10 9 8 pdr8 address: 000008 h pdr9 address: 000009 h bit bit undefined undefined r/w* r/w* pa4 pa3 pa2 pa1 pa0 76 54 3210 pdra address: 00000a h bit undefined r/w*
32 mb90630a series ? port direction registers when pins are used as ports, the register bits control the corresponding pins as follows. 0: input mode 1: output mode bits are set to 0 by a reset. d07 d06 d05 d04 d03 d02 d01 d00 76 54 3210 d17 d16 d15 d14 d13 d12 d11 d10 15 14 13 12 11 10 9 8 d27 d26 d25 d24 d23 d22 d21 d20 76 54 3210 ddr0 address: 000010 h ddr1 address: 000011 h ddr2 address: 000012 h bit bit bit initial value 00000000 b 00000000 b 00000000 b access r/w r/w r/w d37 d36 d35 d34 d33 d32 d31 d30 15 14 13 12 11 10 9 8 d47 d46 d45 d44 d43 d42 d41 d40 76 54 3210 ddr3 address: 000013 h ddr4 address: 000014 h bit bit 00000000 b 00000000 b r/w r/w d57 d56 d55 d54 d53 d52 d51 d50 15 14 13 12 11 10 9 8 ddr5 address: 000015 h bit 00000000 b r/w d67 d66 d65 d64 d63 d62 d61 d60 76 54 3210 d74 d73 d72 d71 d70 15 14 13 12 11 10 9 8 ddr6 address: 000016 h ddr7 address: 000017 h bit bit 00000000 b -----000 b r/w r/w d87 d86 d85 d84 d83 d82 d81 d80 76 54 3210 d97 d96 d95 d94 d93 d92 d91 d90 15 14 13 12 11 10 9 8 ddr8 address: 000018 h ddr9 address: 000019 h bit bit 00000000 b 00000000 b r/w r/w da4 da3 da2 da1 da0 76 54 3210 ddra address: 00001a h bit ---00000 b r/w
mb90630a series 33 ? port resistance registers ? block diagram notes: ? input resistance register r/w controls the pull-up resistor in input mode. 0: pull-up resistor disconnected in input mode. 1: pull-up resistor connected in input mode. the setting has no meaning in output mode (pull-up resistor disconnected). the direction register (ddr) sets input or output mode. ? the pull-up resistor is disconnected in hardware standby or stop mode (spl = 1) (high impedance). ? this function is disabled when using an external bus. in this case, do not write to this register. rd07 rd06 rd05 rd04 rd03 rd02 rd01 rd00 76 54 3210 rdr0 address: 00001c h bit initial value 00000000 b rd17 rd16 rd15 rd14 rd13 rd12 rd11 rd10 15 14 13 12 11 10 9 8 rdr1 address: 00001d h bit 00000000 b rd67 rd66 rd65 rd64 rd63 rd62 rd61 rd60 76 54 3210 rdr6 address: 00001e h bit 00000000 b data register direction register port i/o resistance register pull-up resistor (approx. 50 k w ) internal data bus
34 mb90630a series ? port pin register ? block diagram notes: ? pin register r/w performs open-drain control in output mode. 0: operate as a standard output port in output mode. 1: operate as an open-drain output port in output mode. the setting has no meaning in input mode (output hi-z). the direction register (ddr) sets input or output mode ? the pull-up resistor is disconnected in hardware standby or stop mode (spl = 1) (high impedance). ? this function is disabled when using an external bus. in this case, do not write to this register. ? analog input enable register controls each port 5 pin as follows. 0: port input mode 1: analog input mode set to 1 by a reset. od47 od46 od45 od44 od43 od42 od41 od40 76 54 3210 odr4 address: 00001b h bit initial value 00000000 b data register direction register port i/o pin register internal data bus ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 15 14 13 12 11 10 9 8 ader address: 00001f h bit initial value 11111111 b (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w)
mb90630a series 35 2. uart the uart is a serial i/o port that can be used for clk asynchronous (start-stop synchronization) or clk synchronous communications. the uart has the following features. ? full duplex, double buffered ? supports asynchronous (start-stop synchronization) and clk synchronous data transfer ? supports multi-processor mode ? built-in dedicated baud rate generator ? supports flexible baud rate setting using an external clock ? error detect function (parity, framing, and overrun) ? nrz type transmission signal ? intelligent i/o service support (1) register configuration asynchronous: 9615, 31250, 4808, 2404, 1202 bps clk synchronous: 1 mbps, 500 kbps, 250 kbps, 125 kbps, and 62.5 for a 6, 8, 10, 12, or 16 mhz clock. 8 bits 8 bits scr ssr smr sidr (r)/sodr (w) 15 87 0 (r/w) (r/w) md1 md0 cs2 cs1 cs0 reserved scke soe 76 54 3210 pen p sbl cl a/d rec rxe txe 15 14 13 12 11 10 9 8 d7 d6 d5 d4 d3 d2 d1 d0 76 54 3210 pe ore fre rdrf tdre rie tie 15 14 13 12 11 10 9 8 md div3 div2 div1 div0 15 14 13 12 11 10 9 8 address: 000020 h 000088 h 000089 h 00008a h 00008b h address: 000021 h address: 000022 h address: 000023 h address: 000027 h bit bit bit bit bit serial mode register 0, 1 (smr0, 1) serial control register 0, 1 (scr0, 1) serial input register/ serial output register 0, 1 (sidr/sodr0, 1) serial status register 0, 1 (ssr0, 1) clock division control register (cdcr) cdcr (r/w)
36 mb90630a series (2) block diagram smr register scr register control signals dedicated baud rate generator upper 8/16-bit ppg timer (connected internally) external clock sin0, 1 clock select circuit reception interrupt (to cpu) transmission interrupt (to cpu) reception control circuit start bit counter reception bit counter reception parity counter transmission control circuit transmission start circuit transmission bit counter transmission parity counter reception status detection circuit reception shifter end of reception transmission shifter start of transmission reception error occurrence signal for i 2 os (to cpu) sidr sodr f 2 mc-16 bus md1 md0 cs2 cs1 cs0 scke soe ssr register control signals transmission clock pulses reception clock pulses sot0, 1 pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sck0, 1
mb90630a series 37 3. i/o expansion serial interface this block consists of an 8-bit serial i/o interface that can perform clock synchronous data transfer. either lsb- first or msb-first data transfer can be selected. the following two serial i/o operation modes are available. ? internal shift clock mode: data transfer is synchronized with the internal clock. ? external shift clock mode: data transfer is synchronized with the clock input from the external pin (sck). by manipulating the general-purpose port that shares the external pin (sck), this mode also enables the data transfer operation to be driven by cpu instructions. (1) register configuration (2) register details ? serial mode control status register (smcs) *1: only 0 can be written. *2: only 1 can be written. reading always returns 0. this register controls the transfer operation mode of the serial i/o. the following describes the function of each bit. (a) [bit 3] serial mode selection bit (mode) this bit selects the conditions for starting operation from the halted state. changing the mode during operation is prohibited. the bit is initialized to 0 by a reset. the bit is readable and writable. set to 1 when using the intelligent i/o service. mode operation 0 start when strt is set to 1. [initial value] 1 start on reading from or writing to the serial data register. smd2 smd1 smd0 sie sir busy stop strt 15 14 13 12 11 10 9 8 mode bds soe scoe 76 54 3210 d7 d6 d5 d4 d3 d2 d1 d0 76 54 3210 address: 000025 h 000029 h address: 000024 h 000028 h address: 000026 h 00002a h bit bit bit serial mode control status registers 0, 1 (smcs0, 1) serial data registers 0, 1 (sdr0, 1) smd2 smd1 smd0 sie sir busy stop strt 15 14 13 12 11 10 9 8 mode bds soe scoe 76 54 3210 smcs smcs bit bit initial value 00000010 b ----0000 b address: 000025 h 000029 h address: 000024 h 000028 h initial value (r/w) (r/w) (r/w) (r/w) (r/w* 1 ) (r) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w* 2 )
38 mb90630a series (b) [bit 2] transfer direction selection bit (bds: bit direction select) selects as follows at the time of serial data input and output whether the data are to be transferred in the order from lsb to msb or vice versa. (3) block diagram mode operation 0 lsb-first [initial value] 1 msb-first internal data bus internal data bus (msb-first) d0 to d7 transfer direction selection read write sdr (serial data register) internal clock control circuit shift clock counter interrupt request sin1, 2 sot1, 2 sck1, 2 smd2 smd1 smd0 sie sir busy stop strt mode bds d7 to d0 (lsb-first) 21 0 soe scoe
mb90630a series 39 4. a/d converter the a/d converter converts analog input voltages to digital values. the a/d converter has the following features. ? conversion time: minimum of 5.2 m s per channel (for a 16 mhz machine clock) ? uses rc-type successive approximation conversion with a sample and hold circuit. ? 10-bit resolution ? eight program-selectable analog input channels single conversion mode : selectively convert a one channel. scan conversion mode : continuously convert multiple channels. maximum of 8 program- selectable channels. continuous conversion mode : repeatedly convert specified channels. stop conversion mode : convert one channel then halt until the next activation. (enables synchronization of the conversion start timing.) ? an a/d conversion completion interrupt request to the cpu can be generated on the completion of a/d conversion. this interrupt can activate i 2 os to transfer the result of a/d conversion to memory and is suitable for continuous operation. ? activation by software, external trigger (falling edge), or timer (rising edge) can be selected. (1) register configuration the a/d converter has the following registers. 8 bits 8 bits adcs2 adcr2 adcs1 adcr1 15 87 0 md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 76 54 3210 busy int inte paus sts1 sts0 strt da 15 14 13 12 11 10 9 8 76 54 3210 76 54 3210 9 8 15 14 13 12 11 10 9 8 address: 000036 h address: 000037 h address: 000038 h address: 000039 h bit bit bit bit control status register (adcs1, adcs2) data register (adcr1, adcr2)
40 mb90630a series (2) block diagram av cc avrh avrl an0 an1 an2 an3 an4 an5 an6 an7 mpx sample and hold circuit comparator d/a converter successive approximation register data register a/d control register 1 a/d control register 2 adcr1, 2 adcs1, 2 adtg ppg01 f timer activation trigger activation operating clock prescaler av ss input circuit decoder data bus
mb90630a series 41 5. d/a converter this block is an r-2r type d/a converter with 8-bit resolution. the device contains two d/a converters. the d/a control register controls the output of the two d/a converters independently. (1) register configuration (2) block diagram da07 da06 da05 da04 da03 da02 da01 da00 76 54 3210 da17 da16 da15 da14 da13 da12 da11 da10 15 14 13 12 11 10 9 8 dae0 76 54 3210 dae1 15 14 13 12 11 10 9 8 address: 00003a h address: 00003b h address: 00003c h address: 00003d h bit bit bit bit d/a converter data register 0 (dat0) d/a converter data register 0 (dat1) d/a control register 0 (dacr0) d/a control register 1 (dacr1) f 2 mc-16 bus da 17 da 16 da 15 da 14 da 13 da 12 da 11 da 10 da 07 da 06 da 05 da 04 da 03 da 02 da 01 da 00 dae1 standby control standby control 2r 2r 2r 2r r r r dvr da17 da16 da15 da11 da10 da output channel 1 dae0 2r 2r 2r 2r r r r dvr da07 da06 da05 da01 da00 da output channel 0 2r 2r
42 mb90630a series 6. 8/16-bit ppg this block is an 8-bit reload timer module. the block performs ppg output in which the pulse output is controlled by the operation of the timer. the hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. the ppg has the following functions. ? 8-bit ppg output in two channels independent operation mode: two independent ppg output channels are available. ? 16-bit ppg output operation mode : one 16-bit ppg output channel is available. ? 8+8-bit ppg output operation mode : variable-period 8-bit ppg output operation is available by using the output of channel 0 as the clock input to channel 1. ? ppg output operation : outputs pulse waveforms with variable period and duty ratio. can be used as a d/a converter in conjunction with an external circuit. (1) register configuration channel 0,1 000046 h channel 1 000045 h 15 14 13 12 11 10 9 pen1 pe10 pie1 puf1 md1 md0 reserved 8 (r/w) (r/w) (r/w) (? (r/w) (r/w) (r/w) (? (0) (0) (x) (0) (0) (0) (1) (0) ppg0 operation mode control address: channel 0 000044 h 7654321 pen0 pe00 pie0 puf0 reserved 0 (? (r/w) (? (? (r/w) (r/w) (r/w) (? (0) (x) (x) (0) (0) (0) (1) (x) address: ppgc0 ppgc1 7654321 pcs2 pcs1 pcs0 pcm2 pcm1 pcm0 pe11 pe01 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (0) (0) (0) (0) (0) (0) (0) (0) address: ppgoe ppg1 operation mode control ppg0, 1 output control register read/write initial value read/write initial value read/write initial value 15 14 13 12 11 10 9 8 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (x) (x) (x) (x) (x) (x) (x) (x) read/write initial value channel 0 000041 h address: reload register h prlh0, 1 channel 1 000043 h (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (x) (x) (x) (x) (x) (x) (x) (x) read/write initial value channel 0 000040 h address: reload register l prll0, 1 channel 1 000042 h
mb90630a series 43 (2) block diagram ppg0 output latch pcnt (down-counter) s r q ppg00 output enable ppg01 output enable l/h selector prlbh0 ppgc0 peripheral clock divided by 16 peripheral clock divided by 8 peripheral clock divided by 4 peripheral clock divided by 2 peripheral clock prll0 prlh0 l-side data bus h-side data bus ppg00 ppg01 clear invert pen0 reload channel 1-borrow irq count clock selection timebase counter output main clock divided by 512 l/h select pie 0 puf0 (operation mode control) a/d converter ? 8/16-bit ppg (channel 0)
44 mb90630a series clear invert ppg1 output latch pcnt (down-counter) s r q ppg10 output enable ppg11 output enable l/h selector prlbh1 ppgc1 prll1 prlh1 l-side data bus h-side data bus ppg10 ppg11 pen1 reload channel 0-borrow irq l/h select pie puf uart peripheral clock divided by 16 peripheral clock divided by 8 peripheral clock divided by 4 peripheral clock divided by 2 peripheral clock count clock selection timebase counter output main clock divided by 512 (operation mode control) ? 8/16-bit ppg (channel 1)
mb90630a series 45 7. 8/16-bit up/down counter/timer this block is an up/down counter/timer and consists of six event input pins, two 8-bit up/down counters, two 8- bit reload/compare registers, and their control circuits. (1) main functions ? the 8-bit count register can count in the range 0 to 256d (or 0 to 65535d in 1 16-bit operation mode). ? the count clock selection can select between four different count modes. count modes ? two different internal count clocks are available in timer mode. count clock (at 16 mhz operation) ? in up/down count mode, you can select which edge to detect on the external pin input signal. detected edge ? phase difference count mode is suitable for motor encoder counting. by inputting the a, b, and z phase outputs from the encoder, a high-precision rotational angle, speed, or similar count can be implemented simply. ? two different functions can be selected for the zin pin. zin pin ? compare and reload functions are available and can be used either independently or together. a variable- width up/down count can be performed by activating both functions. compare/reload function ? whether or not to generate an interrupt when a compare, reload (underflow), or overflow occurs can be set independently. ? the previous count direction can be determined from the count direction flag. ? an interrupt can be generated when the count direction changes. timer mode up/down counter mode phase difference count mode ( 2) phase difference count mode ( 8) 125 ns (8 mhz: divide by 2) 1.0 m s (1 mhz: divide by 8) detect falling edges detect rising edges detect both rising and falling edges edge detection disabled counter clear function gate function compare function (output an interrupt when a compare occurs.) compare function (output an interrupt and clear the counter when a compare occurs.) reload function (output an interrupt and reload when an underflow occurs.) compare/reload function (output an interrupt and clear the counter when a compare occurs. output an interrupt and reload when an underflow occurs.) compare/reload disabled
46 mb90630a series (2) register configuration the 8/16-bit up/down counter/timer has the following registers. 8 bits 8 bits reversed area ccrh1 csr1 ccrl1 15 87 0 d07 d06 d05 d04 d03 d02 d01 d00 76 54 3210 d17 d16 d15 d14 d13 d12 d11 d10 15 14 13 12 11 10 9 8 d07 d06 d05 d04 d03 d02 d01 d00 76 54 3210 d17 d16 d15 d14 d13 d12 d11 d10 15 14 13 12 11 10 9 8 cstr cite udie cmpf ovff udff udf1 udf0 76 54 3210 address: 000070 h address: 000071 h address: 000072 h address: 000073 h address: 000074 h 000078 h bit bit bit bit bit up/down count register channel 0 (udcr0) up/down count register channel 1 (udcr1) reload compare register channel 0 (rcr1) reload compare register channel 1 (rcr1) counter status register channel 0, 1 (csr0, 1) ccrh0 ccrl0 reversed area rcr1 udcr1 csr0 rcr0 udcr0 ctut ucre rlde udcc cgsc cge1 cge0 76 54 3210 m16e cdcf cfie clks cms1 cms0 ces1 ces0 15 14 13 12 11 10 9 8 cdcf cfie clks cms1 cms0 ces1 ces0 76 54 3210 address: 000076 h 00007a h address: 000077 h address: 00007b h bit bit bit counter status register channel 0, 1 (ccrl0, 1) counter control register channel 0 (ccrh0) counter control register channel 1 (ccrh1)
mb90630a series 47 (3) block diagram data bus cge1 cge0 c/gs carry cms1 cms0 ces1 ces0 cite udie udf1 udf0 cdcf cfie edge or level detection rcr0 (reload/compare regiater 0) ctut ucre rlde reload control udcc counter clear udcr0 (up/down count regiater 0) cmpf udff ovff prescaler clks cstr up/down count clock selection count clock interrupt output 8 bits 8 bits ain0 bin0 zin0 ? 8/16-bit up/down counter/timer (channel 0)
48 mb90630a series data bus cge1 cge0 c/gs carry cite udie udf1 udf0 cdcf cfie edge or level detection rcr1 (reload/compare register 1) ctut ucre rlde reload control udcc counter clear udcr1 (up/down count register 1) cmpf udff ovff prescaler clks cstr up/down count clock selection count clock interrupt output 8 bits 8 bits ain1 bin1 zin1 cms1 cms0 ces1 ces0 en16 ? 8/16-bit up/down counter/timer (channel 1)
mb90630a series 49 8. clock output control register the clock output outputs the divided machine clock. (1) register configuration (a) [bit 3] cken ckot output enable bit (b) [bits 2, 1, 0] frq2, frq1, frq0 these bits select the output frequency of the clock. mode operation 0 operate as a standard port. 1 operate as the ckot output. frq2 frq1 frq0 output clock f = 16 mhz f = 8 mhz f = 4 mhz 000 f /2 1 125 ns 250 ns 500 ns 001 f /2 2 250 ns 500 ns 1 m s 010 f /2 3 500 ns 1 m s2 m s 011 f /2 4 1 m s2 m s4 m s 100 f /2 5 2 m s4 m s8 m s 101 f /2 6 4 m s8 m s16 m s 110 f /2 7 8 m s 16 m s32 m s 111 f /2 8 16 m s 32 m s64 m s clock control register address: 0003e h 7654321 cken frq2 frq1 frq0 0 (r/w) (r/w) (r/w) (r/w) (? (0) (? (? (? (0) (0) (0) clkr read/write initial value bit
50 mb90630a series 9. dtp/external interrupts the dtp (data transfer peripheral) is a peripheral block that interfaces external peripherals to the f 2 mc-16l cpu. the dtp receives dma and interrupt processing requests from external peripherals and passes the requests to the f 2 mc-16l cpu to activate the intelligent i/o service or interrupt processing. two request levels (h and l) are provided for the intelligent i/o service. for external interrupt requests, generation of interrupts on a rising or falling edge as well as on h and l levels can be selected, giving a total of four types. (1) register configuration (2) block diagram en7 en6 en5 en4 en3 en2 en1 en0 76 54 3210 er7 er6 er5 er4 er3 er2 er1 er0 15 14 13 12 11 10 9 8 lb3 la3 lb2 la2 lb1 la1 lb0 la0 76 54 3210 lb7 la7 lb6 la6 lb5 la5 lb4 la4 15 14 13 12 11 10 9 8 address: 000030 h address: 000031 h address: 000032 h address: 000033 h bit bit bit bit interrupt/dtp enable register (enir) interrupt/dtp source register (eirr) request level setting register (elvr) request level setting register (elvr) 4 4 4 8 4 interrupt/dtp enable register interrupt/dtp source register request level setting register gate request f/f edge detect circuit request input f 2 mc-16 bus
mb90630a series 51 10. 16-bit i/o timer the 16-bit i/o timer consists of one 16-bit free-run timer, four output compare, and two input capture modules. based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs and to measure input pulse widths and external clock periods. (1) a summary of each function ? 16-bit free-run timer ( 1) the 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. the output of the timer/counter is used as the base time for the input capture and output compare. (a) the operating clock for the counter can be selected from four different clocks. four internal clocks ( f /4, f /16, f /32, f /64) (b) interrupts can be generated when a counter value overflow or compare match with compare register 0 occurs (the appropriate mode must be set for a compare match). (c) the counter can be initialized to 0000 h by a reset, software clear, or compare match with compare register 0. ? output compare ( 4) the output compare consists of two 16-bit compare registers, compare output latches, and control registers. the modules can invert the output level and generate an interrupt when the 16-bit free-run timer value matches the compare register value. (a) the four compare registers can be operated independently. each compare register has a corresponding output pin and interrupt flag. (b) the four compare registers can be paired to control the output pins. invert the output pins using the four compare registers. (c) initial values can be set for the output pins. (d) an interrupt can be generated when a compare match occurs. ? input capture ( 2) the input capture consists of two independent external input pins, their corresponding capture registers, and a control register. the value of the 16-bit free-run timer can be stored in the capture register and an interrupt generated when the specified edge is detected on the signal from the external input pin. (a) the edge to detect on the external input signal is selectable. detection of rising edges, falling edges, or either edge can be specified. (b) the two input capture channels can operate independently. (c) an interrupt can be generated on detection of the specified edge on the external input signal. the input capture interrupt can activate the intelligent i/o service.
52 mb90630a series (2) register configuration for the entire 16-bit i/o timer tcdt 15 0 timer data register bit 000066 h tccs timer control status register 000068 h occp0 to 3 15 0 compare register channel 0 to 3 bit 000050, 52, 54, 56 h ocs1/3 ocs0/2 compare control status register channel 0, 2 000058, 5a h ipcp0 to 1 input capture register channel 0, 2 000060, 62 h ics input capture control status register 000064 h 15 0 bit 16-bit free-run timer control logic 16-bit timer compare register 0 compare register 1 compare register 2 compare register 3 capture register 0 capture register 1 output compare 0 output compare 1 output compare 2 output compare 3 input capture 0 tq tq tq tq edge selection edge selection interrupt to each block out 0 out 1 out 2 out 3 in 0 in 1 clear bus ? 16-bit free-run timer ? 16-bit output compare ? 16-bit input capture ? overall block diagram of the 16-bit i/o timer
mb90630a series 53 (3) 16-bit free-run timer the 16-bit free-run timer consists of a 16-bit up-counter and a control status register. the count value of the timer is used as the base time for the input capture and output compare. (a) the count clock can be selected from four different clocks. (b) interrupts can be generated when a counter value overflow occurs. (c) depending on the mode setting, the counter can be initialized when a match occurs with compare register 0 of the output compare. tcdt 15 0 timer data register bit 000066 h tccs timer/counter control status register 000068 h ivf ivfe stop mode clr clk1 clk0 16-bit up-counter divider comparator 0 clock f count value output t15 to t00 interrupt request bus ? register configuration ?block diagram
54 mb90630a series ? register details the count value of the 16-bit free-run timer can be read from this register. the count is cleared to 0000 h by a reset. writing to this register sets the timer value. however, only write to the register when the timer is halted (stop = 1). always use word access. the 16-bit free-run timer is initialized by the following. (a) reset (b) the clear bit (clr) of the control status register (c) a match between the timer/counter value and compare register 0 of the output compare (if the appropriate mode is set) 15 14 13 12 11 10 9 8 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (0) (0) (0) (0) (0) (0) (0) (0) read/write initial value 000067 h address: (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (0) (0) (0) (0) (0) (0) (0) (0) read/write initial value 000066 h address: bit bit t07 t00 t06 t05 t04 t03 t02 t01 t15 t14 t13 t12 t11 t10 t09 t08 data register
mb90630a series 55 (4) output compare the output compare consists of 16-bit compare registers, compare output pins, and a control register. the module can invert the output level and generate an interrupt when the 16-bit free-run timer value matches a compare register value. (a) the two compare registers can be operated independently. the output compare can also be set to control pin output using two compare registers. (b) the initial value of the output pins can be set. (c) an interrupt can be generated when a compare match occurs. ? register configuration ? block diagram 15 0 15 0 000050, 52, 54, 56 h compare registers channel 0 to 3 000058, 59, 5a, 5b h compare control status registers channel 0 to 3 x = 0 to 3 bit bit occp0 to 3 ocsx ocsx icp1 icp0 ice1 ice0 compare control tq control blocks compare 1 interrupt (3) compare regiater 0 (2) compare control compare regiater 1 (3) controller 16-bit timer/counter value (t15 to t00) 16-bit timer/counter value (t15 to t00) tq cmod ote1 oteo compare 0 interrupt (2) out0 (out2) out1 (out3) bus
56 mb90630a series (5) input capture the function of this module is to store the value of the 16-bit free-run timer in a register when the specified edge (rising, falling, or either edge) is detected on the external input signal. the module can also generate an interrupt on detection of the edge. the input capture contains input capture data registers and a control register. each input capture has a corresponding external input pin. (a) three different types of edge detection can be selected. rising edges ( - ), falling edges ( ), or either edge ( - ). (b) an interrupt can be generated on detection of the specified edge on the external input. ? register configuration (for the entire input capture) ? block diagram 15 0 70 000060, 62 h input capture data register x = 0 to 1 000064 h input capture control status register x = 0 to 1 bit bit ipcx icsx capture data register 0 edge detection interrupt 16-bit timer/counter value (t15 to t00) interrupt in 0 capture data register 1 edge detection eg11 eg10 eg01 eg00 icp1 icp0 ice1 ice0 in 1 bus
mb90630a series 57 ? register details the 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input waveform from the corresponding external pin. (always use word access. writing is prohibited.) 15 14 13 12 11 10 9 8 76543210 (r) (r) (r) (r) (r) (r) (r) (r) (x) (x) (x) (x) (x) (x) (x) (x) read/write initial value 000060, 62 h (r) (r) (r) (r) (r) (r) (r) (r) (x) (x) (x) (x) (x) (x) (x) (x) read/write initial value bit bit cp07 cp00 cp06 cp05 cp04 cp03 cp02 cp01 cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 input capture data register
58 mb90630a series 11. watchdog timer the watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase counter as its clock source, a control register, and a watchdog reset controller. the following block diagram shows the structure of both the watchdog timer and timebase timer (see 12. timebase timer). (1) block diagram (2) register configuration wte wt1 wt0 selector 2-bit counter reset control selectror clear tbie tbof i 2 os irq tbr tbc1 tbc0 clear control 2 power-on reset stop mode f/2 1 2 1 12 2 1 13 2 1 14 2 1 15 2 1 16 2 1 17 2 1 18 ......... timebase counter reset output enable clear osc1 osc0 selectror oscillation stabilization delay completion signal 1/2 16 to 1/2 18 (timebase division output) 76543210 0000a8 h bit ponr stbr wrst erst srst wte wt1 wt0 address: watchdog timer control register (wdtc)
mb90630a series 59 12. timebase timer the timebase timer consists of an 18-bit timebase counter (which divides the system clock) and a control register. the carry signal of the timebase counter can generate a fixed period interrupt. all bits of the timebase counter are cleared to zero at power-on, when stop mode is set, or by software (by writing 0 to the tbr bit). the timebase counter continuously increments while an oscillation is input. the timebase counter is also used as the clock source for the watchdog timer and as a timer for the oscillation stabilization delay time. (1) block diagram see (1) block diagram in 11. watchdog timer for the block diagram of the timebase timer. (2) register configuration (3) register details ? tbtc (timebase timer control register) (a) [bit 15] reserved a reserved bit. always set to 1 when writing data to the register. (b) [bit 12] tbie interval interrupt enable bit for the timebase timer. the interrupt is enabled when tbie is 1 and disabled when tbie is 0. initialized to 0 by a reset. the bit is readable and writable. (c) [bit 11] tbof interrupt request flag for the timebase timer. an interrupt request is generated if tbcf goes to 1 when tbie is 1. the bit is set to 1 at fixed intervals set by the tbc1 and 0 bits. clear by writing 0, transition to stop or hardware standby mode, or a reset. writing 1 has no meaning. read as 1 by read-modify-write instructions. (d) [bit 10] tbr clears all bits of the timebase counter to 0. writing 0 to the tbr bit clears the timebase counter. writing 1 to the tbr bit is meaningless. reading from the tbr bit results in 1. (e) [bit 9, 8] tbc1, 0 set a timebase timer interval. the bits are initialized to 00 by resetting. these bits are readable and writable. setting of timebase timer interval tbc1 tbc0 interval time when base frequency is 4 mhz 0 0 1.024 ms 0 1 4.096 ms 1 0 16.384 ms 1 1 131.072 ms 15 14 13 12 11 10 9 8 0000a9 h bit reserved tbie tbcf tbr tbc1 tbc0 address: timebase timer control register (tbtc) 15 14 13 12 11 10 9 8 0000a9 h bit reserved tbie tbcf tbr tbc1 tbc0 address: initial value x--00000 b (w) (r/w) (r/w) (w) (r/w) (r/w)
60 mb90630a series 13. external bus pin control circuit the external bus pin control circuit controls the external bus pins required to extend the cpus address/data bus outside the device. (1) register configuration (2) block diagram 0000a6 h 0000a5 h 15 14 13 12 11 10 9 icr1 icr0 hmr1 hmr0 lmr1 lmr0 8 (? (w) (w) (w) (w) (w) (? (w) (0) (0) (0) (1) (1) (? (0) (? address: arsr 7654321 e23 e22 e21 e20 e19 e18 e17 e16 0 (w) (w) (w) (w) (w) (w) (w) (w) (0) (0) (0) (0) (0) (0) (0) (0) address: hacr auto-ready function selection register external address output control register read/write initial value read/write initial value 0000a7 h 15 14 13 12 11 10 9 cke rye hde icbs hmbs wre lmbs 8 (w) (w) (w) (w) (w) (w) (w) (? (0) (0) (0) (0) (0) (1/0) (? (0) address: epcr bus control signal selection register read/write initial value bit bit bit p3 p2 p1 p0 access control access control p0 address control data control p0 data p0 direction p3 rb
mb90630a series 61 4. low-power control circuits (cpu intermittent operation function, oscillation stabilization delay time, and clock multiplier function) the following operation modes are available: pll clock mode, pll sleep mode, timer mode, main clock mode, main sleep mode, stop mode, and hardware standby mode. operation modes other than pll clock mode are classified as low power consumption modes. in main clock mode and main sleep mode, the device operates on the main clock only (osc oscillator clock). the pll clock (vco oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the operating clock. in pll sleep mode and main sleep mode, the cpus operating clock only is stopped and other elements continue to operate. in timer mode, only the timebase timer operates. stop mode and hardware standby mode stop the oscillator. these modes maintain existing data with minimum power consumption. the cpu intermittent operation function provides an intermittent clock to the cpu when register, internal memory, internal resource, or external bus access is performed. this function reduces power consumption by lowering the cpu execution speed while still providing a high-speed clock to internal resources. the pll clock multiplier ratio can be set to 1, 2, 3, or 4 by the cs1, 0 bits. the ws1, 0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop mode or hardware standby mode. (1) register configuration 0000a0 h 7654321 stp slp spl rst reserved cg1 cg0 reserved 0 (r/w) (w) (r/w) (w) (r/w) (w) (? (? (0) (0) (0) (0) (1) (1) (0) (0) address: lpmcr low-power consumption mode register read/write initial value 0000a1 h 15 14 13 12 11 10 9 reserved mcm ws1 ws0 reserved mcs cs1 cs0 8 (r/w) (? (r/w) (r) (r/w) (r/w) (? (r/w) (1) (0) (1) (1) (1) (1) (0) (1) address: ckscr clock select register read/write initial value bit bit
62 mb90630a series (2) block diagram main clock (osc oscillator) mcm mcs cs1 cs0 cg1 cg0 slp stp pll multiplier circuit 1234 1/2 cpu clock selector cycle selection circuit for the cpu intermittent operation function standby control circuit rst release hstactivate osc1 osc0 oscillation stabilization delay time selector spl internal reset generator rst pin high impedance control circuit cpu clock generator peripheral clock generator timebase timer 2 4 2 13 2 15 2 18 clock input 2 19 2 16 2 14 2 12 lpmcr lpmcr ckscr ckscr ckscr lpmcr lpmcr 0/9/17/33 intermittent cycle selection cpu clock peripheral clock hst pin interrupt request or rst timebase clock pin hi-z rst pin internal rst to watchdog timer wdgrst f 2 mc-16 bus ? low-power consumption control circuit and clock generator
mb90630a series 63 main mcs=1 mcm=1 cs1/0=xx main ? pllx mcs=0 mcm=1 cs1/0=xx pll1 ? main mcs=1 mcm=0 cs1/0=00 pll2 ? main mcs=1 mcm=0 cs1/0=01 pll3 ? main mcs=1 mcm=0 cs1/0=10 pll4 ? main mcs=1 mcm=0 cs1/0=11 pll 1 multiplier mcs=0 mcm=0 cs1/0=00 pll 2 multiplier mcs=0 mcm=0 cs1/0=01 pll 3 multiplier mcs=0 mcm=0 cs1/0=10 pll 4 multiplier mcs=0 mcm=0 cs1/0=11 (1) (2) (3) (6) (7) (7) (7) (7) (6) (6) (6) (5) (4) (6) (1) mcs bit cleared (2) pll clock oscillation stabilization delay complete and cs1/0=?0 (3) pll clock oscillation stabilization delay complete and cs1/0=?1 (4) pll clock oscillation stabilization delay complete and cs1/0=?0 (5) pll clock oscillation stabilization delay complete and cs1/0=?1 (6) mcs bit set (including a hardware standby or watchdog reset) (7) pll clock and main clock synchronized timing power-on ? state transition diagram for clock selection
64 mb90630a series 5. delayed interrupt generation module the delayed interrupt generation module is used to generate the task switching interrupt. interrupt requests to the f 2 mc-16l cpu can be generated and cleared by software using this module. (1) register configuration (2) register details delayed interrupt request register (dirr) the dirr register controls generation and clearing of delayed interrupt requests. writing 1 to the register generates a delayed interrupt request. writing 0 to the register clears the delayed interrupt request. the register is set to the interrupt cleared state by a reset. either 0 or 1 can be written to the reserved bits. however, considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for register access. (3) block diagram 00009f h 15 14 13 12 11 10 9 r0 8 address: bit delayed interrupt request register (dirr) 00009f h 15 14 13 12 11 10 9 r0 8 address: bit initial value -------0 b (r/w) delayed interrupt generate/clear decoder interrupt latch f 2 mc-16 bus
mb90630a series 65 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1: av cc , avrh, and avrl must not exceed v cc . similarly, it must not exceed avrh and avrl. *2: v i and v o must not exceed v cc + 0.3 v. *3: the maximum output current must not be exceeded at any individual pin. *4: the average output current is the rating for the current from an individual pin averaged over 100 ms. *5: the average total output current is the rating for the current from all pins averaged over 100 ms. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v av cc * 1 v ss C 0.3 v ss + 7.0 v avrh, avrl* 1 v ss C 0.3 v ss + 7.0 v program voltage v pp v ss C 0.3 v input voltage* 2 v i v ss C 0.3 v cc + 0.3 v output voltage* 2 v o v ss C 0.3 v cc + 0.3 v l level (maximum) output current* 3 i ol 15ma l level (average) output current* 4 i olav 50ma l level total (maximum) output current s i ol 100ma l level total (average) output current* 5 s i olav 50ma h level (maximum) output current* 3 i oh C15ma h level (average) output current* 4 i ohav C50ma h level total (maximum) output current s i oh C100 ma h level total (average) output current* 5 s i ohav C50ma power consumption p d +400 mw operating temperature t a C40 +85 c storage temperature t stg C55 +150 c
66 mb90630a series 2. recommended operating conditions (v ss = 0.0 v) warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 2.7 5.5 v for normal operation 2.7 5.5 v to maintain statuses in stop mode h level input voltage v ih 0.7 v cc v cc + 0.3 v other than v ihs v ihs 0.8 v cc v cc + 0.3 v hysteresis inputs v ihm v cc C 0.3 v cc + 0.3 v l level input voltage v il v ss C 0.3 0.3 v cc v other than v ils v ils v ss C 0.3 0.2 v cc v hysteresis inputs v ilm v ss C 0.3 v ss + 0.3 v operating temperature t a C40 +85 c
mb90630a series 67 3. dc characteristics (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) *1: hysteresis input pins: rst , hst *2: current values are provisional and are subject to change without notice to allow for improvements to the characteristics and similar. parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih v cc = +5.0 v 10% 0.7 v cc v cc + 0.3 v v ihs 0.8 v cc v cc + 0.3 v *1 v ihm v cc C 0.3 v cc + 0.3 v l level input voltage v il v cc = +5.0 v 10% 0.7 v cc v cc + 0.3 v v ils 0.8 v cc v cc + 0.3 v *1 v ilm v ss C 0.3 v ss + 0.3 v h level output voltage v oh v cc = +4.5 v 10% i oh = C4.0 ma v cc C 0.5 v v cc = +2.7 v i oh = C1.6 ma v cc C 0.3 v l level output voltage v ol v cc = +4.5 v 10% i oh = C4.0 ma 0.4v v cc = +2.7 v i oh = C2.0 ma 0.4v pull-up resistor r pull rst 22110k w power supply current* 2 i cc v cc v cc = +5.0 v 10% f c = 16 mhz 6080ma i ccs 2035ma i cc v cc v cc = +3.0 v 10% f c = 10 mhz 1540ma i ccs 1015ma i cch v cc = +5.0 v 10% 20 m a input pin capacitance c in other than v cc and v ss 10pf input leak current i il p73, 74 p86, 87 v cc = 5.5 v v ss < v i < v cc C10 10 m a leak current for open-drain outputs i leak p50 to p57 0.110 m a
68 mb90630a series 4. ac characteristics (1) clock timing ?when v cc = 5.0 v 10% (v cc = 4.5 v to +5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) ?when v cc = 2.7 v (min.) (v cc = 4.5 v to +5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. clock frequency f c x0, x1 3 16 mhz clock cycle time t c x0, x1 62.5 333 ns input clock pulse width p wh , p wl x0 10 ns the duty ratio should be in the range 30 to 70% input clock rise time and fall time t cr , t cf x0 5 ns internal operating clock frequency f cp 1.516mhz internal operating clock cycle time t cp 62.5 333 ns parameter symbol pin name condition value unit remarks min. max. clock frequency f c x0, x1 3 10 mhz clock cycle time t c x0, x1 100 333 ns input clock pulse width p wh , p wl x0 20 ns the duty ratio should be in the range 30 to 70% input clock rise time and fall time t cr , t cf x0 5 ns internal operating clock frequency f cp 1.58mhz internal operating clock cycle time t cp 100 333 ns 0.8 v cc 0.2 v cc t cf t cr t c p wh p wl ? clock timing
mb90630a series 69 the ac characteristics are for the following measurement reference voltages. 5.5 4.5 2.7 816 v cc voltage (v) normal operation range 3.3 3 1.5 internal clock f cp (mhz) 34 8 16 24 32 16 12 9 8 4 multiply by 4 multiply by 3 no multiplier oscillation clock f c (mhz) internal clock f cp (mhz) relationship between the oscillation frequency and internal operating clock frequency relationship between the internal operating clock frequency and suply voltage note: low voltage operation down to 2.7 v is also assured for the evaluation tools. pll operation assurance range multiply by 2 multiply by 1 ? pll operation assurance range hysteresis input pins 0.8 v cc 0.2 v cc other than hysteresis or md input pins 0.7 v cc 0.3 v cc output pins 2.4 v 0.8 v ? input signal waveform ? output signal waveform
70 mb90630a series (2) clock output timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) (3) reset and hardware standby inputs (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. cycle time t cyc clk v cc = 5.0 v 10% 62.5 ns clk - ? clk t chcl 20 ns parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst 4 machine cycle hardware standby input time t hstl hst 4 machine cycle t cyc t chcl clk 0.8 v 2.4 v 2.4 v rst hst 0.2 v cc 0.2 v cc t rstl , t hstl
mb90630a series 71 (4) power-on reset (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) note: the above values are the values required for a power-on reset. parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc 30ms power supply cut-off time t off v cc 1ms holding ram data 2.25 v t r 0.2 v v cc 5.0 v 2.7 v v ss v cc the gradient should be no more than 50 mv/ms. abrupt changes in the power supply voltage may cause a power-on reset. when changeing the power supply voltage during operation, suppress variations in the voltage and ensure that the voltage rises smoothly, as shown in the following figure. also, do not use the pll clock when varying the voltage. however, the supply voltage can be changed when using the pll clock if the voltage drops by less than 1 mv/s.
72 mb90630a series (5) bus timing (read) (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. ale pulse width t lhll ale t cp /2 C20 ns valid address ? ale time t avll multiplexed address t cp /2 C25 ale ? address valid time t llax multiplexed address t cp /2 C15 ns valid address ? rd time t avrl multiplexed address t cp C15 valid address ? valid data input t avdv multiplexed address 5 t cp /2 C60 ns rd pulse width t rlrh rd 3 t cp /2 C20 ns rd ? valid data input t rldv d15 to d00 3 t cp /2 C60 ns rd - ? data hold time t rhdx 0ns valid address ? valid data input t avdv 0ns rd - ? ale - time t rhlh rd , ale t cp /2 C15 ns rd - ? address valid time t rhax address, rd t cp /2 C10 ns valid address ? clk - time t avch address, clk t cp /2 C20 ns rd ? clk - time t rlch rd , clk t cp /2 C20 ns clk ale rd address read data t rhdx 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc a19 to a16 ad15 to ad00 t avch t rlrh t avrl t lhll t avll t rhlh t rhax t rldv t avdv t rlch t llax
mb90630a series 73 (6) bus timing (write) (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. valid address ? wr time t avwl a19 to a00 t cp C15 ns valid address ? rd time t avrl a23 to a00 t cp /2 C15 ns wr pulse width t wlwh wr 3 t cp /2 C20 ns rd pulse width t rlrh rd 3 t cp /2 C20 ns valid data output ? wr - time t dvwh d15 to d00 3 t cp /2 C20 ns wr - ? data hold time t whdx d15 to d00 20 ns wr - ? address valid time t whax a19 to a00 t cp /2 C10 ns wr - ? ale - time t whlh wr , ale t cp /2 C15 ns wr ? clk - time t wlch wr l , wrh , clk t cp /2 C20 ns clk ale wr (wrl, wrh) address write data 0.8 v 2.4 v a19 to a16 ad15 to ad00 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t wlch t avwl t wlwh t whlh t whax t whdx t dvwh
74 mb90630a series (7) ready input timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) note: use the auto-ready function if the rdy setup time is too short. parameter symbol pin name condition value unit remarks min. max. rdy setup time t ryhs rdy v cc = 5.0 v 10% 45 ns v cc = 3.0 v 10% 70 ns rdy hold time t ryhh 0ns t ryhs t ryhs t ryhs t ryhh clk ale rd/wr rdy (when one wait states are inserted) rdy (when wait states are not inserted) 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 2.4 v 2.4 v
mb90630a series 75 (8) hold timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) note: after reading hrq, more than one cycle is required before changing hak . parameter symbol pin name condition value unit remarks min. max. pin floating ? hak time t xhal hak 30t cp ns hak - ? pin valid time t hahv hak t cp 2 t cp ns hrq high impedance hak pin t xhal t hahv
76 mb90630a series (9) uart timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) notes: ? these are the ac characteristics for clk synchronous mode. ?c l is the load capacitance connected to the pin at testing. ?t cp is the machine cycle period (unit: ns). parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc 8 t cp ns sck ? sot delay time t slov v cc = +5.0 v 10% C80 80 ns c l = 80 pf+1ttl for the internal shift clock mode output pin v cc = +3.0 v 10% C120 120 ns valid sin ? sck - t ivsh v cc = +5.0 v 10% 100 ns v cc = +3.0 v 10% 200 ns sck - ? valid sin hold time t shix v cc = +5.0 v 10% 60 ns v cc = +3.0 v 10% 120 ns serial clock h pulse width t shsl 4 t cp ns c l = 80 pf+1ttl for the external shift clock mode output pin serial clock l pulse width t slsh 4 t cp ns sck ? sot delay time t slov v cc = +5.0 v 10% 150 ns v cc = +3.0 v 10% 200 ns valid sin ? sck - t ivsh v cc = +5.0 v 10% 60 ns v cc = +3.0 v 10% 120 ns sck - ? valid sin hold time t shix v cc = +5.0 v 10% 60 ns v cc = +3.0 v 10% 120 ns
mb90630a series 77 sck sot sin t scyc t slov t ivsh t shix 2.4 v 0.8 v cc 0.8 v 0.8 v 2.4 v 0.8 v 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t slov t ivsh t shix t shsl 0.8 v cc 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc ? internal shift clock mode ? external shift clock mode
78 mb90630a series (10) i/o extended serial timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) notes: ? these are the ac characteristics for clk synchronous mode. ?c l is the load capacitance connected to the pin at testing. ?t cp is the machine cycle period (unit: ns). ? the values in the table are target values. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc 8 t cp ns c l = 80 pf+1ttl for the internal shift clock mode output pin sck ? sot delay time t slov v cc = +5.0 v 10% 80 ns v cc = +3.0 v 10% 160 ns valid sin ? sck - t ivsh t cp ns sck - ? valid sin hold time t shix t cp ns serial clock h pulse width t shsl v cc = +5.0 v 10% 230 ns c l = 80 pf+1ttl for the external shift clock mode output pin max. 2 mhz v cc = +3.0 v 10% 460 ns serial clock l pulse width t slsh v cc = +5.0 v 10% 230 ns v cc = +3.0 v 10% 460 ns sck ? sot delay time t slov 2 t cp ns valid sin ? sck - t ivsh t cp ns sck - ? valid sin hold time t shix 2 t cp ns
mb90630a series 79 sck sot sin t scyc t slov t ivsh t shix 2.4 v 0.8 v cc 0.8 v 0.8 v 2.4 v 0.8 v 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t slov t ivsh t shix t shsl 0.8 v cc 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc ? internal shift clock mode ? external shift clock mode
80 mb90630a series (11) timer output timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) (12) trigger input timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. sck - ? t out change time t to out0 to out3 v cc = +5.0 v 10% 30 ns ppg00 to ppg11 v cc = +3.0 v 10% 80 ns parameter symbol pin name condition value unit remarks min. max. input pulse width t trgh t trgl atg , irq0 to irq7 in0, in1 5 t cp ns 2.4 v 2.4 v 0.8 v t to clk out0 to out3 ppg0 to ppg1 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t trgh t trgl atg, irq0 to irq7 in0, in1
mb90630a series 81 (13) up/down counter (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. ain input 1 pulse width t ahl ain0, ain1 bin0, bin1 8 t cyl ns ain input 0 pulse width t all 8 t cyl ns bin input 1 pulse width t bhl 8 t cyl ns bin input 0 pulse width t bll 8 t cyl ns ain - ? bin - time t aubu 4 t cyl ns bin - ? ain time t buad 4 t cyl ns ain ? bin time t adbd 4 t cyl ns bin ? ain - time t bdau 4 t cyl ns bin - ? ain - time t buau 4 t cyl ns ain - ? bin time t aubd 4 t cyl ns bin ? ain time t bdad 4 t cyl ns ain ? bin - time t adbu 4 t cyl ns zin input 1 pulse width t zhl zin0, zin1 4 t cyl ns zin input 0 pulse width t zll 4 t cyl ns
82 mb90630a series t ahl t aubu t buad t bhl t bhl t buau t aubd t ahl t zhl t zll t all t bdad t adbu t bll t bll t adbd t bdau t all ain bin bin bin zin 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc
mb90630a series 83 5. a/d converter electrical characteristics (av cc = v cc = +2.7 v to +5.5 v, av ss = v ss = 0.0 v, 2.7 v avrh C avrl, t a = C40 c to +85 c) *1: for v cc = +5.0 v 10% and a 16 mhz machine clock *2: for v cc = +3.0 v 10% and an 8 mhz machine clock *3: the current when the a/d converter is not operating or the cpu is in stop mode (for v cc = av cc = avrh = +5.0 v). notes: ? the error increases proportionally as |avrh C avrl| decreases. ? the output impedance of the external circuits connected to the analog inputs should be in the following range. output impedance of external circuit < approx. 10 k w ? if the output impedance of the external circuit is too high, the sampling time for the analog voltage may be too short. (sampling time = 3.8 m s (corresponds to 16 mhz internal operation if the multiplier is 4.)) note: the above values are for reference only. parameter symbol pin name value unit min. typ. max. resolution 10 10 bit total error 3.0 lsb linearity error 2.0 lsb differential linearity error 1.5 lsb zero transition error v ot an0 to an7 C1.5 +0.5 +2.5 lsb full scale transition error v fst an0 to an7 avrh C3.5 avrl C1.5 avrh +0.5 lsb conversion time 5.12* 1 m s 8.12* 2 m s analog port input current i ain an0 to an7 10 m a analog input voltage v ain an0 to an7 avrl avrh v reference voltage avrh avrl + 2.7 av cc v avrl 0 avrh C 2.7 v power supply current i a av cc 5ma i ah av cc 5* 3 m a reference voltage supply current i r avrh 200 m a i rh avrh 5* 3 m a variation between channels an0 to an7 4 lsb comparator analog input r on1 r on2 c 1 c 0 r on1 = 1.5 k w (approx.) (v cc = 5.0 v) r on2 = 0.5 k w (approx.) (v cc = 5.0 v) r on3 = 0.5 k w (approx.) (v cc = 5.0 v) r on4 = 0.5 k w (approx.) (v cc = 5.0 v) c 0 = 60 pf (approx.) c 1 = 4 pf (approx.) r on3 r on4 sample and hold circuit ? model of the analog input circuit
84 mb90630a series 6. a/d converter glossary ? resolution the change in analog voltage that can be recognized by the a/d converter. if the resolution is 10 bits, the analog voltage can be resolved into 2 10 = 1024 steps. ? total error the deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and noise. ? linearity error the deviation between the actual conversion characteristic of the device and the line linking the zero transition point (00 0000 0000 ? 00 0000 0001) and the full scale transition point (11 1111 1110 ? 11 1111 1111). ? differential linearity error the variation from the ideal input voltage required to change the output code by 1 lsb. digital output 1111 1111 1111 1110 0000 0001 0000 0000 0000 0010 v ot v nt v (n+1)t v fst (1lsb n + v ot ) analog input linearity error 1lsb = 1022 v fst ?v ot linearity error = 1lsb v nt ?(1lsb n + v ot ) [lsb] 11 11 00 00 00 1lsb v (n+1)t ?v nt ?1 [lsb] differential linearity error =
mb90630a series 85 7. 8-bit d/a converter electrical characteristics (v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) note: dv ss must be connected at v ss = 0.0 v. parameter symbol pin name value unit remarks min. typ. max. resolution 8 8 bit differential linearity error C0.9 0.9 lsb absolute accuracy 1.2 % conversion time 10 20 m s the load capacitance = 20 pf analog reference power supply voltage dvrhv ss + 1.7 v cc vdv ss = v ss = 0.0 v reference power supply current (when operating) i d dvrh 1.0 1.5 ma current consumption at conversion reference power supply current (when stopped) i dh dvrh 10 m a current consumption when stopped analog output impedance da0 28 k w
86 mb90630a series n example characteristics v oh (v) v cc = +5.0 v i oh ( ma ) ? 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 v oh ? i oh ? ? ? v cc = +4.0 v v cc = +3.0 v v cc = +2.7 v v cc = +3.5 v t a = +25 c v cc = +4.5 v v ol (v) v cc = +4.5 v v cc = +5.0 v i ol (ma) 8 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 v ol i ol 46 2 v cc = +4.0 v v cc = +3.0 v v cc = +2.7 v v cc = +3.5 v t a = +25 c 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 23 456 t a = +25 c v in ?v cc 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 23 456 t a = +25 c v in ?v cc v ihs v ils v ihs : threshold when input voltage in hysteresis characteristics is set to ??level v ils : threshold when input voltage in hysteresis characteristics is set to ??level (1) h level output voltage (2) l level output voltage (3) h level input voltage/l level input voltage (cmos input) (4) h level input voltage/l level input voltage (hysteresis input)
mb90630a series 87 i cc (ma) i cc ? cc 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 12.5 mhz f cp = 8 mhz f cp = 4 mhz t a = +25 c i ccs (ma) i ccs ? cc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 12.5 mhz f cp = 8 mhz f cp = 4 mhz t a = +25 c i a (ma) i a ?v cc 3.0 4.0 5.0 6.0 av cc (v) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = +25 c f cp = 16 mhz i r (ma) i r ?vr 3.0 4.0 5.0 6.0 avr (v) 0.30 0.20 0.10 0 t a = +25 c f cp = 16 mhz 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1000 r (k w ) v cc (v) 100 10 2.5 t a = +25 c r? cc (5) power supply current (f cp = internal operating clock frequency) (5) pull-up resistance
88 mb90630a series n instructions (340 instructions) table 1 explanation of items in tables of instructions item meaning mnemonic upper-case letters and symbols: represented as they appear in assembler. lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction. # indicates the number of bytes. ~ indicates the number of cycles. m : when branching n : when not branching see table 4 for details about meanings of other letters in items. rg indicates the number of accesses to the register during execution of the instruction. it is used calculate a correction value for intermittent operation of cpu. b indicates the correction value for calculating the number of actual cycles during execution of the instruction. (table 5) the number of actual cycles during execution of the instruction is the correction value summed with the value in the ~ column. operation indicates the operation of instruction. lh indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. z : transfers 0. x : extends with a sign before transferring. C : transfers nothing. ah indicates special operations involving the upper 16 bits in the accumulator. * : transfers from al to ah. C : no transfer. z : transfers 00 h to ah. x : transfers 00 h or ff h to ah by signing and extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). * : changes due to execution of instruction. C : no change. s : set by execution of instruction. r : reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : instruction is a read-modify-write instruction. C : instruction is not a read-modify-write instruction. note: a read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
mb90630a series 89 table 2 explanation of symbols in tables of instructions (continued) symbol meaning a 32-bit accumulator the bit length varies according to the instruction. byte : lower 8 bits of al word : 16 bits of al long : 32 bits of al:ah ah al upper 16 bits of a lower 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 direct addressing physical direct addressing bit 0 to bit 15 of addr24 bit 16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) imm4 imm8 imm16 imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address
90 mb90630a series (continued) table 3 effective address fields note: the number of bytes in the address extension is indicated by the + symbol in the # (number of bytes) column in the tables of instructions. symbol meaning rel branch specification relative to pc ear eam effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list code notation address format number of bytes in address extension * 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
mb90630a series 91 table 4 number of execution cycles for each type of addressing note: (a) is used in the ~ (number of states) column and column b (correction value) in the tables of instructions. table 5 correction values for number of cycles used to calculate number of actual cycles notes: (b), (c), and (d) are used in the ~ (number of states) column and column b (correction value) in the tables of instructions. when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. table 6 correction values for number of cycles used to calculate number of program fetch cycles notes: when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for worst case calculations. code operand (a) number of register accesses for each type of addressing number of execution cycles for each type of addressing 00 to 07 ri rwi rli listed in tables of instructions listed in tables of instructions 08 to 0b @rwj 2 1 0c to 0f @rwj + 4 2 10 to 17 @rwi + disp8 2 1 18 to 1b @rwj + disp16 2 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (c) word (d) long number of cycles number of access number of cycles number of access number of cycles number of access internal register +01+01+02 internal memory even address internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 even address on external data bus (16 bits) odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 external data bus (8 bits) +11+42+84 instruction byte boundary word boundary internal memory +2 external data bus (16 bits) +3 external data bus (8 bits) +3
92 mb90630a series table 7 transfer instructions (byte) [41 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g b operation l h a h istnzvc rm w mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov ri, ear mov ri, eam mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah /mov @a, t xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) +disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z x x x x x x x x x x C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * * * * * * * C * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90630a series 93 table 8 transfer instructions (word/long word) [38 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw dir, a movw addr16, a movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw al, ah /movw @a, t xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C movl a, ear movl a, eam movl a, #imm32 movl ear, a movl eam, a 2 2+ 5 2 2+ 4 5+ (a) 3 4 5+ (a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C C C C C C C C C C C
94 mb90630a series table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g b operation l h a h istnzvc rm w add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) Cimm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C C C * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) +(ear) word (a) ? (a) +(eam) word (a) ? (a) +imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) Cimm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 6 7+ (a) 4 6 7+ (a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) +imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) Cimm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
mb90630a series 95 table 10 increment and decrement instructions (byte/word/long word) [12 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+ (a) 7 9+ (a) 4 0 4 0 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * mnemonic # ~ r g boperation l h a h istnzvc rm w cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (ah) C (al) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (ah) C (al) word (a) ? (ear) word (a) ? (eam) word (a) ? imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (a) ? (ear) word (a) ? (eam) word (a) ? imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
96 mb90630a series table 12 multiplication and division instructions (byte/word/long word) [11 instructions] *1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. *2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when the result is zero or when an overflow occurs, and 2 (b) normally. *7: (c) when the result is zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not zero. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not zero. *12: 4 when word (ear) is zero, and 12 when word (ear) is not zero. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g b operation l h a h istnzvc rm w divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 1 0 1 0 0 1 0 0 1 0 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
mb90630a series 97 table 13 logical 1 instructions (byte/word) [39 instructions ] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C * C C C C * C C C C * C C * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C C * C C C C C * C C C C C * C C *
98 mb90630a series table 14 logical 2 instructions (long word) [6 instructions] table 15 sign inversion instructions (byte/word) [6 instructions] table 16 normalize instruction (long word) [1 instruction] *1: 4 when the contents of the accumulator are all zeroes, 6 + (r0) in all other cases (shift count). note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ea xorl a, eam 2 2+ 2 2+ 2 2+ 6 7+ (a) 6 7+ (a) 6 7+ (a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ r g boperation l h a h istnzvc rm w neg a neg ear neg eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ rg b operation l h a h istnzvc rm w nrml a, r0 2 * 1 1 0 long (a) ? shift until first digit is 1 byte (r0) ? current shift count CCCCCC*CC C
mb90630a series 99 table 17 shift instructions (byte/word/long word) [18 instructions] *1: 6 when r0 is 0, 5 + (r0) in all other cases. *2: 6 when r0 is 0, 6 + (r0) in all other cases. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g b operation l h a h istnzvc rm w rorca rolc a rorcear rorceam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+ (a) 3 5+ (a) * 1 * 1 * 1 0 0 2 0 2 0 1 1 1 0 0 0 2 (b) 0 2 (b) 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C * C * C C C asrwa lsrwa/shrw a lslw a/shlw a asrwa, r0 lsrwa, r0 lslw a, r0 1 1 1 2 2 2 2 2 2 * 1 * 1 * 1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * r * * * * * * * * * * C C C C C C * * * * * * C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 2 2 2 * 2 * 2 * 2 1 1 1 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C * * C * * * * * * C C C * * * C C C
100 mb90630a series table 18 branch 1 instructions [31 instructions] *1: 4 when branching, 3 when not branching. *2: (b) + 3 (c) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) r branch address. *7: save (long word) to stack. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation l h a h istnzvc rm w bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 11+ (a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15, (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 to 15 (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15 (pcb) ? (eam) 16 to 23 word (pc) ? addr0 to 15, (pcb) ? addr16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90630a series 101 table 19 branch 2 instructions [19 instructions] *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: retrieve (word) from stack *8: retrieve (long word) from stack *9: in the cbne/cwbne instruction, do not use the rwj+ addressing mode. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation l h a h istnzvc rm w cbne a, #imm8, rel cwbnea, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel* 9 cwbneear, #imm16, rel cwbneeam, #imm16, rel* 9 dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti link #local8 unlink ret * 7 retp * 8 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 * 1 * 1 * 2 * 3 * 4 * 3 * 5 * 6 * 5 * 6 20 16 17 20 15 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (eam) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * C C C C C C C C C C C C C C s s s s * C C C C C C C C C C C C C C C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * C C C C C C C C * C C C C C C C C C C C * C * C C C C C C C C C
102 mb90630a series table 20 other control instructions (byte/word/long word) [36 instructions] *1: pcb, adb, ssb, usb, and spb : 1 state dtb, dpr : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) C 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: pop count (c), or push count (c) *5: pop count or push count. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation l h a h istnzvc rm w pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 * 3 3 3 4 * 2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 * 1 1 1 1 1 1 1 1 1 0 0 0 * 5 0 0 0 * 5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) +2 word (ah) ? ((sp)), (sp) ? ( sp) +2 word (ps) ? ((sp)), (sp) ? ( sp) +2 (rlst) ? ((sp)), (sp) ? (sp) +2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? (sp) +ext (imm8) word (sp) ? (sp) +imm16 byte (a) ? (brgl) byte (brg2) ? (a) no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no flag change prefix code for common register bank C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90630a series 103 table 21 bit manipulation instructions [21 instructions] *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: undefined count *5: until condition is satisfied note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation l h a h istnzvc rm w movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 * 1 * 1 * 2 * 1 * 1 * 2 * 3 * 4 * 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 5 * 5 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C
104 mb90630a series table 22 accumulator manipulation instructions (byte/word) [6 instructions] table 23 string instructions [10 instructions] m: rw0 value (counter value) n: loop count *1: 5 when rw0 is 0, 4 + 7 (rw0) for count out, and 7 n + 5 when match occurs *2: 5 when rw0 is 0, 4 + 8 (rw0) in any other case *3: (b) (rw0) + (b) (rw0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) n *5: 2 (rw0) *6: (c) (rw0) + (c) (rw0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) n *8: 2 (rw0) note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w swap swapw/xchw al, ah ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a) 0 to 7 ? (a) 8 to 15 word (ah) ? (al) byte sign extension word sign extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ r g b operation l h a h istnzvc rm w movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 5 * 5 * 5 * 5 * 5 * 3 * 3 * 4 * 4 * 3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval (@ah+) C al, counter = rw0 byte retrieval (@ahC) C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/ movswi movswd scweq/ scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 8 * 8 * 8 * 8 * 8 * 6 * 6 * 7 * 7 * 6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval (@ah+) C al, counter = rw0 word retrieval (@ahC) C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
mb90630a series 105 n ordering information model package remarks MB90632APFV mb90634apfv mb90p634apfv 100-pin plastic lqfp (fpt-100p-m05) mb90632apf mb90634apf mb90p634apf 100-pin plastic qfp (fpt-100p-m06) mb90p634a supports es alone.
106 mb90630a series n package dimensions c 1994 fujitsu limited f100008-3c-2 "a" "b" 0.10(.004) 0.53(.021)max 0.18(.007)max details of "a" part 0 10 details of "b" part 12.35(.486) ref 16.30?.40 (.642?016) 0.05(.002)min (stand off) 0.15?.05(.006?002) index 23.90?.40(.941?016) 20.00?.20(.787?008) 17.90?.40 14.00?.20 (.551?008) (.705?016) 0.13(.005) m 18.85(.742)ref 22.30?.40(.878?016) 1 30 31 50 51 80 81 100 0.25(.010) 0.30(.012) 0.65(.0256)typ 0.30?.10 (.012?004) lead no. 0.80?.20 (.031?008) 3.35(.132)max (mounting height) (mounting height) c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.00?.20(.630?008)sq 14.00?.10(.551?004)sq 0.50(.0197)typ .007 ?001 +.003 ?.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?004 +.008 ?.10 +0.20 1.50 .005 ?001 +.002 ?.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.50?.20(.020?008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.10?.10 (.004?004) (stand off) 0~10 lead no. (mouting height) (mounting height) dimensions in mm (inches) 100-pin plastic lqfp (fpt-100p-m05) dimensions in mm (inches) 100-pin plastic qfp (fpt-100p-m06)
mb90630a series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0004 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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